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Field-Effect Transistors
Published in Nassir H. Sabah, Electronics, 2017
CMOS circuits have important advantages in both analog and digital applications. A CMOS amplifier having a diode-connected depletion-type MOSFET load gives higher gain at a lower supply voltage, and occupies a smaller area on the chip than one that uses the same driver transistor but with a passive resistive load. A CMOS transmission gate allows having control voltages at the two extremes of signal voltages and provides a resistance in the conducting state that is more nearly constant for different inputs.
Post-layout simulation of an ultra-low-power OTA using DTMOS input differential pair
Published in International Journal of Electronics Letters, 2018
Mohammad Khaleqi Qaleh Jooq, Mostafa Miralaei, Abbas Ramezani
Many low-voltage and low-power design techniques have been developed to solve the high level of threshold voltage, such as bulk-driven and floating-gate MOSFETs, sub-threshold design, level shifting technique and DTMOS method (Blalock, Allen, & Rincon-Mora, 1998; Hasler & Lande, 2001; Hu, 1993; Uygur & Kuntman, 2013; Wang, Clhoun, & Chandracasan, 2006). DTMOS techniques (presented by Assederaghi in 1994 (Assederaghi et al., 1994)) paved the way to the problems of the threshold voltage of the conventional analogue integrated circuits (Stockstad & Yoshizawa, 2002). This technique improves the specifications of a conventional complementary metal-oxide-semiconductor (CMOS) amplifier such as power supply voltage and power consumption with a proper open-loop gain and unity gain bandwidth (Lehmann & Cassia, 2001). A DTMOS transistor circuit symbol is shown in Figure 1.
Scanning the Issue
Published in IETE Journal of Research, 2018
The paper on “A multiple-feedback UWB LNA with low noise and improved linearity”, presents the design of a low noise CMOS amplifier with good linearity property for ultra-wide band applications in the 3.1-10.6 GHz band. A multiple-feedback network is designed to provide good bandwidth extension and compact chip size. The design also caters for noise and distortion cancellation in the input stage. The overall amplifier performance is presented in terms of gain, power dissipation, chip size and other specifications in simulation experiments.
DTMOS Based Low Power Adaptively Biased Fully Differential Transconductance Amplifier with Enhanced Slew-Rate and its Filter Application
Published in IETE Journal of Research, 2023
Mihika Mahendra, Shweta Kumari, Maneesha Gupta
In [1], presented topology utilizes current mirrors based two extra current sources and positive feedback loop to increase the tail current that results in improved driving capability, with slew-rate of 0.25 V/μS at the supply voltage ±5 V using 5 μm technology, but its performance is limited by the mismatched effects due to positive feedback loop, which results in a significant amount of distortion for applied small input signals. A CMOS amplifier implementation using 5 μm technology with an additional static and dynamic biasing circuit to inject an extra bias current during the operation of a small and large signal is proposed in [2] operates at ±5 V, offers the enhanced slew-rate of +41/−44 V/μS at the cost of large power dissipation and the active area which often results in stray capacitances and degrades the frequency response. The dynamically biased output stage based on the switched-capacitor approach, implemented using 1.2 μm CMOS technology at ±1.2 V is depicted in [3], provides a slew-rate of 0.54 V/μS with a large active area for the amplifier. The fully differential operational transconductance amplifier using a current subtractor biasing technique implemented [6] in 0.35 μm technology with a supply rail of ±1.5 V has demonstrated limited slew-rate of 17 V/μS. The adaptive biasing using PMOS high-swing cascade current subtractor, fabricated in 90 nm technology presented in [7] operates at ±0.6 V provides limited slew-rate of 37 V/μS with increased silicon area. In [8] two current source using translinear loop topology connected in the positive feedback loop of an amplifier have been proposed using 0.18 μm technology at ±0.6 V supply voltage, to increase the tail current by reducing the mismatch effects reported in [1] and provides improved slew-rate as +68/−68 V/μS at the cost of large silicon area and poor gain bandwidth product. An adaptive bias current circuit based on the current monitor, current comparison, and current amplification is proposed in [9] using 0.18 μm CMOS technology with the supply voltage of 3 V, which provides a very restricted slew-rate of +0.20/−0.25 V/μS with reduced frequency response. The proposed current mirror amplifier in [10] with current starving technique boosts the dc gain of the amplifier, but due to starving drain current from the output transistors slew-rate is sacrificed to a great extent, to control this, current feeding technique is implemented as a slew-rate enhancement technique using 0.18 μm CMOS process and achieves the slew-rate as 2.8 V/μS with limited gain bandwidth, it operates at ±1.8 V. In [11], improved recycling folded cascade amplifier with two different slewing paths during the slewing phase have been proposed using a 0.18 μm process with ±1.2 V supply voltage, this added auxiliary circuit provides slew-rate of 101 V/μS at the cost of limited dc gain and additional die area.