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Basic concepts
Published in Zdravko Karakehayov, Knud Smed Christensen, Ole Winther, Embedded Systems Design with 8051 Microcontrollers, 2018
Zdravko Karakehayov, Knud Smed Christensen, Ole Winther
Logically, the microprocessor controls the address bus. The data bus lines are bidirectional. The microprocessor can read data from a memory component (the PIO’s registers might be viewed as a part of the memory), or it can send data out to the memory. Memory components such as RAM or ROM take over the data bus when the microprocessor reads. Therefore, the output buffers of the devices must be somewhat different. In addition to the two logic states (high output level and low output level), they possess an extra state termed OFF state (high impedance state). When the three-state buffer is in the OFF state, you could think that the IC and the bus are no longer joined by any physical bond. The microcomputer shown in Figure 1.16 will work properly if only the devices attached to the bus obey the following restriction: only one IC can open its output buffers to drive the bus at a time. The situation when two or more devices activate their outputs is named bus contention. Overriding the bus discipline by bus contention will result in significant currents where two outputs try to establish different levels on a line of the bus.
Automatic Test Pattern Generation
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
Kwang-Ting (Tim) Cheng, Li-C. Wang
Property Checking An ATPG engine can find an example for proving that the circuit violates certain properties or, after exhausting the search space, can prove that no such example exists and thus that the circuit meets certain properties [96,97]. One example of this is checking for tristate bus contention, which occurs when multiple tristate bus drivers are enabled and their data is not consistent. Figure 22.15 shows a sample application. If the ATPG engine finds a test for the output stuck-at-0 fault, the test found will be the vector that causes bus contention. If no test exists, the bus can never have contention. Similarly, ATPG can check to see if a bus is floating — all tristate bus drivers are disabled — simply by checking for a vector that sets all enable lines to an inactive state.
Automatic Test Pattern Generation
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
Kwang-Ting (Tim) Cheng, Li-C. Wang, Huawei Li, James Chien-Mo Li
An ATPG engine can find an example for proving that the circuit violates certain properties or, after exhausting the search space, can prove that no such example exists and thus that the circuit meets certain properties [188,189]. One example of this is checking for tristate bus contention, which occurs when multiple tristate bus drivers are enabled and their data are not consistent. Figure 22.21 shows a sample application. If the ATPG engine finds a test for the output stuck-at-0 fault, the test found will be the vector that causes bus contention. If no test exists, the bus can never have contention. Similarly, ATPG can check to see if a bus is floating—all tristate bus drivers are disabled—simply by checking for a vector that sets all enable lines to an inactive state.
A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison
Published in International Journal of Computers and Applications, 2023
K. Gaffour, M. K. Benhaoua, A. H. Benyamina, H. E. Zahaf
The evolution of semiconductor technology allows integrating more and more Intellectual Properties (IPs) onto the same chip to meet the high computational demand of recent complex applications. In general, these applications are compounded of a set of dependent (communicating) tasks that can run in parallel onto different IPs. When these tasks exchange information, they generate traffic on communication media. Network-on-Chip (NoC) paradigm has been proposed to cope with bus contention and congestion problems in traditional communication supports that have been designed basically for single core architectures [1].