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Semiconductor memory, input and output, and peripheral circuits
Published in D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader, Mechatronics, 2018
D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader
The contents of a masked ROM are determined during its manufacture. The structure of part of a masked ROM memory is shown in Fig. 12.2a. The devices marked a and b are MOS transistors, which are described in section 13.3.2, whose operation can be considered as a simple switch. For example, the transistor at the intersection of the word line and the D2 data line operates as follows. When the word line is enabled and therefore at a high logic level, the transistor will be switched on and effectively connect the data line to 0 V. The transistor at the top of the data line has been configured such that its electrical characteristics are similar to a resistor, which simply limits the current drawn from the power line Vcc when the memory cell transistor is turned on. Hence, in places in the memory array where the transistor is not connected, as in the transistor marked c, or when the word line is not enabled, the output of the data line is a high logic level. The contents of the ROM are therefore determined by the presence or absence of connections to the transistors at the intersection of the word lines and the data lines. Each transistor corresponds to a memory cell, or bit cell because it also corresponds to a single bit of memory. The ROM can be fabricated with each cell transistor initially making a connection to the word line, and then the required bit pattern can be implemented by selectively etching away the connections to those transistors which are to represent a logic 1 memory bit.
Dynamic Random Access Memory (DRAM)
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
Another feasible design is to use the 2T gain cell, as shown in Figure 3.33(a). There are two transistors in one bit cell: the reading transistor and the writing transistor. The gate capacitor of the reading transistor becomes the storage node, which could be charged or discharged by the writing transistor. The stored electrons on the gate capacitor could suppress the channel current of the reading transistor, as it equivalently increases the threshold voltage. A small amount of charges on the gate could result in significant changes of the channel current as a result of the transconductance amplification. However, the gate capacitor has a limited capacitance thus cannot hold the charges for a long time (typically less than 1 ms if implemented with silicon logic process [9]). Therefore, the writing transistor should be ultra-low leakage. One promising candidate for the writing transistor is the semiconducting oxide-channel-based transistor, which could offer ultra-low off-state current density (<1 fA/μm) thanks to its wide bandgap. Recent progresses in In-Ga-Zn-Oxide (IGZO) [10] and In-W-Oxide (IWO) [11] offers the unique advantages as these oxide-channel-based transistors could be fabricated on top of the logic transistor at the BEOL, and thus no significant area penalty with 3D folded layout. Figure 3.33(b) summarizes the representative 2T gain cell design, highlighting the orders of magnitude improved retention by using oxide channel for the writing transistor’s channel. It should be noted that silicon is still preferred for the reading transistor’s channel for faster access as Si still outperforms the oxides by 5× to 10× in terms of electron mobility.
Networks
Published in Geoff Lewis, Communications Technology Handbook, 2013
Ethernet system. This is a half-duplex send-receive system based on a highway or bus. This is constructed from a length of 50 ohms co-axial cable which must be terminated at each end in a suitable load. The typical maximum cable length is 2.5 km, but this can be extended by interfacing other similar networks via suitable gateways. The maximum number of nodes or stations permitted on each sector is 1024. The raw data rate is 10 Mbit/s and each node on the network is driven by a separate 20 MHz clock. The Manchester code format is used to ensure that the clocks are synchronised to the data stream. The bit cell is divided into two, the second part containing the true bit value and the first its complement. Network access control uses the carrier sense, mutliple access/collision detect technique. All nodes listen continually to the network to detect a suitable time to transmit data. If two stations detect the same clear period, each will transmit and then detect a collision. Both will continue to transmit for a further 80 ns so that all nodes can recognise that a data collision has occurred. The transmitting nodes then back-off for a random period before trying to retransmit. If a further collision occurs both back-off for a longer period. After 16 attempts, the node concerned logs a system failure. The transmission frame format consists of a maximum of 1526 bytes made up as follows. A clock synchronising preamble of alternate 1s and 0s consisting of seven bytes, followed by a similar eighth byte but ending with two 1s, the last 1 representing a start bit. Destination and source address fields each of six bytes. The first bit in each is described as a multicast bit. When this is set to 1 in the destination address, all terminals within a group or block must respond to the message. In the source address, this bit is always set 0. Although only 1024 stations are permitted per network and these could be addressed by just ten bits, the 47 bits available could address more than 1.4 x 1014 unique nodes. This has been arranged so that stations in different networks have different addresses and that owners of the patent rights can exert some control over the development of Ethernet. Twenty-three bits of the address field are thus allocated by Ethernet, leaving the remaining 24 bits for user allocation. The following two bytes are used to identify the data type and length. The data field is variable between the limits of 46 and 1500 bytes. Each frame ends with four bytes of cyclical redundancy check (CRC). At the receiver, the bits following the start bit are stripped off and the CRC recalculated and compared with that transmitted, any disagreement being reported to the local microprocessor.
Single-Ended 8T SRAM cell with high SNM and low power/energy consumption
Published in International Journal of Electronics, 2022
Javad Mohagheghi, Behzad Ebrahimi, Pooya Torkzadeh
where read SNM and hold SNM are the static noise margins during the read and hold operations. Write SNM is the write margin of the cell. Read delay is the read access time. Pleakage is the average leakage power. Pread and Pwrite are dynamic powers of the cell during the read and write operations, respectively. The area used here is the bit-cell area normalised to the 6T SRAM cell. Table 7 lists the EQM of SRAM cells considered in this work at different supply voltages. We observe that the proposed 8T SRAM cell has the highest EQM at all supply voltages. The EQM of the proposed 8T SRAM cell, at a supply voltage of 0.5 V, is 84x, 12.4x, 45.8x, 5x, 37.7x and 3.8x compared to the cells 6T, WRE8T, ST-1, SB9T, 12T, and 11T respectively. Therefore, the proposed 8T SRAM cell is an attractive choice considering the overall performance along with the least area overhead.
Resistive Random Access Memory: A Review of Device Challenges
Published in IETE Technical Review, 2020
Varshita Gupta, Shagun Kapur, Sneh Saurabh, Anuj Grover
RRAM array can be implemented as a 1 selector–1 resistor (1S1R) structure. In a 1 transistor–1 resistor (1T1R) structure, as shown in Figure 6(a), the selector is a front-end-of-line (FEoL) device such as a CMOS transistor, a BJT or a gate-all-around transistor [81]. However, the selectors severely increase the bit cell area, the process cost and the complexity [81]. Therefore, structures utilizing back-end-of-line (BEoL) devices called cross-point arrays, shown in Figure 6(b), are considered. In cross-point arrays, RRAMs are placed at each intersection of the word-lines and the bit-lines. These structures integrate the BEoL selector in the RRAM stack, thus achieving a high bit cell density [81]. One such BEoL selector device is the field-assisted superlinear threshold (FAST) selector [82]. The FAST selector based device exhibits excellent performance, a small switching slope and a high current drivability. Several other devices including mixed-ionic-electronic-conduction (MIEC) materials and varistor-type bidirectional switches have also been explored as BEoL selector devices [83,84].
Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications
Published in International Journal of Electronics, 2019
Venkata Rao Tirumalasetty, Madhusudhan Reddy Machupalli
Previously proposed techniques, new 14-transistor (14T) 1-bit adder (Vesterbacka, 1999) utilises more than one rationale style for their realisation. In the same way, the hybrid pass-logic (HPSC) (Moaiyeri, Mirzaee, Navi, Nikoubin, & Kavehei, 2010) full adder, new HPSC (Jiang, Al-Sheraidah, Wang, Sha, & Chung, 2004) full adder and hybrid – CMOS adder (Navi, Maeen, et al., 2009; Tung, Hung, Shieh, & Huang, 2007) are utilising more than one rationale style for their realisation. In such HPSC circuit, XOR and XNOR circuits were concurrently created by pass transistor logic by utilising just six transistors, furthermore, utilised in CMOS module to deliver full-swing outputs of the 1-bit adder cell however at the cost of the increased transistor count and diminished speed. These adders, for the most part, do not have the driving abilities. Their execution as a 1-bit cell is excellent, however as the measure of chain expands, the execution decreases radically. In spite of the fact that the hybrid styles offer promising execution, the majority of these hybrid logic adders experienced a poor driving capacity issue and their execution debases definitely in the cascaded mode of operation if the appropriately deliberate buffers are not incorporated.