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Published in Philip A. Laplante, Comprehensive Dictionary of Electrical Engineering, 2018
arithmetic operation ethic were an inspiration to many contemporary scientists. arbiter a unit that decides when multiple requestors may have access to a shared resource. arbitrary reference frame a two-dimensional space that rotates at an unspecified angular velocity . In electric machines/power system analysis, an orthogonal coordinate axis is established in this space upon which fictitious windings are placed. A linear transformation is established in which the physical variables of the system (voltage, current, flux linkage) are referred to variables of the fictitious windings. See also transformation equations, rotor reference frame, stationary reference frame, synchronous reference frame. arbitration ARC See bus arbitration. arcing ground a ground fault on a power line which alternately clears and restrikes, causing high, repetitive voltage surges. ARCP See auxiliary resonant commutated pole converter. area See control area.
Efficient and Low-Power NoC Router Architecture
Published in Choi Jung Han, Iniewski Krzysztof, High-Speed and Lower Power Technologies, 2018
Arbiters are commonly used to allocate and access shared resources. Whenever a resource (such as a buffer, channel or a switch-port) is shared, an arbiter is required to assign the access to the resource at a particular time. A wormhole v-VC router was presented in Section 9.1, where the router arbiter module has a switch allocator consisting of two sets of simple arbiters. A simple arbiter arbitrates among a group of requesters for a single resource, as illustrated in the form of a symbol for an n-input in the right side of Figure 9.5. The arbiter accepts n requests (r0, r1,…, rn−1), arbitrates among the asserted request lines, selects an ri for service, and then asserts the corresponding grant line gi. Arbiters can be categorized on the basis of fairness (weak, strong or FIFO) arbiters [1, 24]. For a weak fairness arbiter, every request is eventually granted. The requests of a strong fairness arbiter are granted equally often. The requests of FIFO fairness are granted on a first come, first served basis. In terms of priority, the arbiters can be grouped into fixed and variable priority architectures. For a fixed-priority arbiter, the priority of requests is established in a linear order. Round Robin (RR) is a well-known variable priority arbiter. The functionality of an RR arbiter can be explained in this way: a request that is most recently granted will have the lowest priority in the next arbitration cycle. The RR arbiters are simple, easy to implement, and they are also starvation-free. When the input requests are large in number, the structure of an RR arbiter grows, requiring larger chip area, higher power consumption, and longer crit ical path delay [1].
Recursive Challenge Feed Arbiter Physical Unclonable Function (RC-FAPUF) In 180nm Process For Reliable Key Generation In IOT Security
Published in IETE Technical Review, 2023
Raveendra Podeti, Sreehari Rao Patri, Muralidhar Pullakandam
The APUF presented in [7–10] comprises two n-stage Multiplexers (Mux) connected parallelly as chains that provoke the arbiter to generate a 1-bit response. It has been extensively investigated as a strong PUF among previously disclosed PUF designs. Based on the input challenge bit, two Muxes are arranged as a twist or straight-through construction. The response bit is evaluated by differentiating the arrival times of the delay paths using an arbiter, such as a Flip-Flop (FF) [11–13], which should change between devices due to the PVs. A large number of CRPs are generated by Double Arbiter PUFs (DAPUFs) [14,15] to improve the security of machine learning attacks. An XoR Feed Arbiter Physical Unclonable Function (XFAPUF) [16] and Feed Forward (FF) XoR PUF [17] are presented to overcome the degraded reliability bottleneck in the security implementation. A compact architecture Flip-Flop (FF)-APUF, designed to achieve decent reliability properties, is presented in [18,19] to offer more resistance for security. Ring-oscillator PUFs [20,21], and Static Random Access Memory (SRAM) PUFs [22] are only a few examples of popular weak PUF concepts. Aside from memory, Ultra-energy-efficient energy temperature PUF [23,24], Low-power sub-threshold PUF [25,26], and Multiple-Valued Logic (MVL) [27] comparators are designed to achieve energy efficiency and low power consumption regarding PVs evaluated in either current mode or voltage mode. A novel architecture Bistable Ring PUF (BRPUF) [28] is presented that is made up of inverters that can able to generate large CRP space.
Comparative Analysis of Delay-Based and Memory-Based Physical Unclonable Functions
Published in IETE Technical Review, 2022
Priti S. Lokhande, Sangeeta Nakhate
For several PUF designs running on both FPGA and ASIC platforms, the metrics and hardware resource consumption are compared in Table 2 [30]. Given that it is difficult to compare different PUF designs directly on an FPGA or ASIC platform, this provides a general overview of the predicted uniqueness and reliability of various PUF designs. It can be observed that SRAM PUF, Latch PUF, Flip-flop PUF, Buskeeper PUF, BR PUF, RO PUF and Subthreshold APUF have uniqueness values close to the ideal (50%) as compared to APUF, Feedforward APUF, Improved APUF, 2–1 Double Arbiter PUF and Flip-flop based APUF where uniqueness value deviates significantly. However, the reliability is approaching the ideal value of 100% for delay-based PUF including RO PUF, CRO PUF, APUF, Subthreshold APUF, Improved APUF and Flip-flop-based APUF as compared to memory-based PUF. Figures 10 and 11 represents the histograms for uniqueness and reliability, respectively for different types of PUF.
Survey on the benefits of using memristors for PUFs
Published in International Journal of Parallel, Emergent and Distributed Systems, 2022
Muayad J. Aljafar, John M. Acken
The authors of [54] proposed a hybrid CMOS-memristor-based XOR/XNOR gate as a building block for implementing an arbiter PUF that maps an N-bit challenge into a 1-bit response. The authors of [57] proposed a challenge-dependent stage delay PUF. The circuit consists of two parallel strings of memristors, i.e. two delay lines of memristors. Any stage of two delay lines is grounded through two MOSFETs controlled by two different challenge bits. At the end of delay lines, there is a D flip-flop arbiter initialized to logic 1. The arbiter determines the faster of two signals simultaneously propagated at the other end of the circuit. In [61], a PUF was built as a parallel string of memristors. The authors modified the previous circuit architecture [57] by moving the CMOS challenge programming transistor from connecting the memristor to the ground to be parallel to the memristors (Figure 7). This modification aimed to prevent cryptoanalysis attacks. The circuit operates in two phases: challenge application and response generation. In the challenge application phase, control signal Ctrl is high preventing the voltage levels at the input terminals of the arbiter to rise. In the response generating phase, control signal Ctrl is low to allow the voltage pulses to propagate along both delay paths. In [71], the number of response bits was increased by adding RS NAND latches, and in [72], the resilient of the circuit to modeling attacks was improved by increasing the variations (i.e. increasing the number of memristors per transistor). Recall that in [66], a time-delay RRAM-based PUF was proposed utilizing 2:1 multiplexers, rather than XOR gates, for diverting the racing pulse based on applied challenge bit.