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Hardware Architecture of IoT and Wearable Devices
Published in Mohammad Ayoub Khan, Internet of Things, 2022
In this chapter, the author has proposed a wide range of hardware architecture for wearable systems incorporating the IoT as communication mainstream mechanism. The chapter details about the different communication protocols and their usability as per different applications and power range requirements. The power and range plays a major role in selection of the protocols for implementing efficient data exchange mechanism. Further the author discussed about the power harvesting advances which have become very handy for wearable solutions. The power requirements are also addressed with the help of new era circuit design techniques to have special power aware circuits for longer and better life and performance. The adiabatic circuit design techniques prove to be very effective in this era where longer battery life trading operating speed becomes handy for wearable systems. The foldable battery and circuits further assist in the advances of the system technologies. In this chapter, the author has provided a comprehensive system view, that should be considered for implementation of better and efficient wearable devices.
Investigation of Homo and Hetero-Junction Double-Gate Tunnel-FET-Based Adiabatic Inverter Circuits
Published in IETE Journal of Research, 2023
M. Pown, S. Sandeep, B. Lakshmi
The adiabatic circuit requires trapezoidal or sinusoidal clocks to reduce the power dissipation. The sinusoidal waveform can be generated with higher energy efficiency than trapezoidal waveform. Hence, the sinusoidal power clocked adiabatic inverter circuits can be found more suitable for the design of low power and optimal performance circuits. In this section, the static adiabatic inverter circuits (QSERL, CEPAL and GFCAL) and the dynamic adiabatic inverter circuits (CAL, PAL and SCAL) are constructed using homo and hetero-junction-based DG-TFETs. These circuits are evaluated by means of two-phase sinusoidal clock. This type of clock is easy to generate compared to trapezoidal clock and produces a well-defined output. The fundamental difference between static and dynamic logic is that the output follows the power clock in dynamic logic, whereas the output is constant in static [3,18]. This is, due to the fact, that the charging and discharging diodes in static logic circuits helps to keep the output constant. In static circuits, the sense amplifier circuit or the latch network pushes the output to follow the power clock.