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CMOS Technology for Wireless Applications
Published in Krzysztof Iniewski, Wireless Technologies, 2017
Semiconductor technologies are usually referred to by the lithography node, designated by its minimum feature length, e.g., 90 nm CMOS. As lithographic dimensions shrink in advanced CMOS nodes, increasing performance, illustrated by increasing fT, presents great opportunities for radio frequency (RF) designers. Figure 18.1 shows published values of fT for silicon n-channel FETs (NFETs) along with the 2003 International Technology Roadmap for Semiconductors (ITRS) projection [1,2]. These data show performance comparable with III–V devices and inverse scaling with gate lengths to 27 nm. A similar plot of fMAX data in Figure 18.2 also shows increasing performance but with considerable variability in published results due to the sensitivity of power gain extraction to parasitic impedances and inconsistencies in de-embedding techniques applied to the measured data. These figure of merits (FOMs) imply that usable gain at conventional wireless application frequencies (~800 MHz–5 GHz) is achievable in CMOS technology nodes beginning at 0.25 μm. In fact, a survey of product announcements or conference publications [3,4] will provide many examples of active work.
Technology CAD for DFM
Published in Chinmay K. Maiti, Introducing Technology Computer-Aided Design (TCAD), 2017
With 45 nm processes, it is imperative to develop a systematic TCAD-based methodology to design, characterize, and optimize manufacturability to increase yield. As the manufacturability of a process technology may be evaluated by the process window, defined as the area between the lower and upper limits of the critical process variables that yields acceptable device performance. The transition to 90 nm technology proved to be extremely challenging, and it is expected to worsen at 65 nm and 45 nm. Beyond pure CMOS, bipolar-based technologies target ever-increasing analog and mixed-signal IC performance, with a strong impact on parametric yield. This trend has spurred the need for innovative advanced process control methodologies reliant on an improved understanding of the correlation between process variables and electrical device parameters.
Introduction to Physical Design
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar
These are not the only issues facing the designer. In sub-90 nm technologies, manufacturability issues have come to the forefront, and many of them are seen to impact physical design. Traditionally, design and manufacturing inhabited different worlds, with minimal handoffs between the two, but in light of issues related to subwavelength lithography and planarization, a new area of physical design has opened up, where manufacturability has entered the equation. The explosion in mask costs associated with these issues has resulted in the emergence of special niches for field programmable gate arrays (FPGAs) for lower performance designs and for fast prototyping; physical design problems for FPGAs have their own flavors and peculiarities.
Comprehensive Design and Timing Analysis for High speed Master Slave D Flip-Flops using 18 nm FinFET Technology
Published in IETE Journal of Research, 2021
N. Shylashree, Varchas S. Bharadwaj, D. Yashas, Vinayak Kulkarni, Ajay Bharadwaj, Vijay Nath
The evaluation of the power consumed and delay between the CLK-to-Q of types of D Flip-Flops has been analyzed in [8]. The circuits in this work have been constructed using 90 nm CMOS technology. A modern D Flip-Flop architecture utilizing improved Self Voltage Level technique has been suggested in [9] to reduce power consumption due to standby leakage currents.