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Time and power randomization for ECC power analysis resistant design
Published in Amir Hussain, Mirjana Ivanovic, Electronics, Communications and Networks IV, 2015
Elliptic Curve Cryptography (ECC) currently has become a cryptographic algorithm with maximum security of single bit key among the public key cipher. Its security is based on elliptic curve discrete logarithm problem (Zhang 2005). Since the cryptographic algorithm implementation should rely on hardware, the security of a cryptographic system not only depends on the algorithms and protocols, but also on the implementation security. The power analysis attack could obtain key information on the cryptographic algorithm by analysis on the power consumption during cryptographic equipment working process, which causes a great threat to the cryptographic system, avoiding solving math problems (Mangard et al. 2010). Therefore, it is of great significance to design the power analysis resistance for the ECC system
Layers of Security for Active RFID Tags
Published in Syed Ahson, Mohammad Ilyas, RFID Handbook, 2017
Shenchih Tung, Swapna Dontharaju, Leonid Mats, Peter J. Hawrylak, James T. Cain, Marlin H. Mickle, Alex K. Jones
Power analysis techniques measure or monitor power consumption of a cryptosystem by physically probing a ground pin [10]. These analysis techniques have been classified into two sets: simple power analysis (SPA) and differential power analysis (DPA) [10]. The accuracy of performing SPA can be easily affected by the signal-noise-ratio (SNR) on the probed pin. However, the DPA technique not only measures power consumption of a cryptosystem, but also requires a statistical analysis based on the collected power consumption information. Thus, it can minimize the effect of SNR because it differentiates output power traces.
MOS switch-based DPA-resistant GF(28) modulo multiplier
Published in International Journal of Electronics Letters, 2018
Pravin Zode, Raghavendra Deshmukh
Whenever data is processed in gates, it generates a typical power dissipation pattern. In CMOS logic, power trace is depend on input data swing for 1→0 transition and 0→1 transition and no swing for 0→0, 1→1 transition. Attacks on cryptographic circuits are based on power analysis measurement while performing operation. These computational powers have traces of input bit transitions. By analysing these traces input bits are evaluated by statistical process. These power traces are analysed by several methods like simple power analysis (SPA) and differential power analysis (DPA) to exploit secret data. SPA is a simple power analysis based on analysis of processing power and interpretation of secret by observation. These attacks attempt to retrieve secret data on single power trace. Whereas in DPA, an attacker computes the intermediate values within cryptographic computations by statistically analysing power traces collected from multiple cryptographic operations. In practice, attacker has detail knowledge of implementation of cryptographic algorithm of device on which attack is to be performed.
Design and verification of improved CMERE against power analysis attacks
Published in Cyber-Physical Systems, 2020
Hridoy Jyoti Mahanta, Abhilash Chakraborty, Ajoy Kumar Khan
Most of the previous works in this particular field of countering power analysis attacks follows either of the two approaches: blinding the exponent with a random number or randomising the bits of the exponent or the execution of the algorithm itself.