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Uniprocessor Computers
Published in Vivek Kale, Parallel Computing Architectures and APIs, 2019
Modern computing systems can be expressed in terms of the reference model described in Figure 1.1. The highest level of abstraction is represented by the API, which interfaces applications to libraries and/or the underlying OS. The application binary interface (ABI) separates the OS layer from the applications and libraries, which are managed by the OS. The ABI covers details such as low-level data types, alignment, and call conventions, and defines a format for executable programs. System calls are defined at this level. This interface allows the portability of applications and libraries across OSs that implement the same ABI. At the bottom layer, the model for the hardware is expressed in terms of the ISA, which defines the instruction set for the processor, registers, and memory, and interrupts management. The ISA is the interface between the hardware and software, and it is important to the OS developer (system ISA) and developers of applications who directly manage the underlying hardware (user ISA).
Performance Evaluation Methods for Multiprocessor System-on-Chip Design
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
Ahmed Jerraya, Iuliana Bacivarov
A CPU module is a hardware module executing a specific instruction set. It is defined by an instruction set architecture (ISA) detailing the implementation and interconnection of the various functional units, the set of instructions, register utilization, and memory addressing.
Power–Performance Trade-Offs in Design of SoCs
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Victor Zyuban, Philip Strenski
Finally, scaling the processor core microarchitecture and, possibly instruction set architecture (ISA), is one more way for trading power and performance. This method involves changing machine organization, such as pipeline depth, issue width, the set of functional units, bypasses, number of ports and entries in queues and register files, the sizes of branch predictors, and other structures of the microarchitecture. Scaling microarchitecture is even a more powerful method for power–performance trade-offs than voltage and circuit scaling, but it is more difficult to quantify and optimize, and can only be used at early stages of the design. A concept of architectural complexity was introduced in Zyuban [19] to analyze power–performance trade-offs at the ISA and microarchitectural levels. It has been demonstrated that architectural complexity cannot only be measured but also set as a design target [10].
Performance optimization of energy harvesting solutions for 0.18um CMOS circuits in embedded electronics design
Published in Cogent Engineering, 2020
The micro-architecture level considers the integration of many of the underlying fundamental device technologies. Transistor technologies and silicon processes are combined into useful blocks such as memory, control, and arithmetic that together form computational device, often a processor or an accelerator. The scope for that integrated device is very broad, including ultralow power embedded devices, through general-purpose processors, up to high-performance network-on-chip components. Current manufacturing of semiconductor devices has hit a fundamental efficiency limit called the “energy wall” that prevents reduction of energy consumption when transistor size scales down for forthcoming technology nodes. Both at small-scale Embedded Systems and at a large-scale HPC/Data centers (Din et al., 2014; Lu et al., 2011). The ultimate limits from architecture designs are almost impossible to drive, but based on current technology, there is general agreement by academia and industry that new architectures are more promising to significantly reduce power consumption than improving the energy consumption of the basic switching device in the circuit. The amount of energy consumption from a circuit architecture design for a given CMOS technology node is heavily dependent on how specific (i.e., optimized for a single or few tasks) or how general (i.e., undertake many different computations) a design has to deliver. Applications Specific Integrated Circuits (ASICs) designed for a single task can be optimized proving the lowest energy consumption, but such designs have no flexibility and cannot be reprogrammed. For microprocessors or microcontrollers that must be able to undertake a wide range of tasks, optimization to reduce energy consumption is significantly more difficult. Micro-architecture exploits what is physically possible with contemporary technology and presents an interface through which other hardware and software can use the device. In hardware terms, this interface is, of course, physical and will typically obey a specified protocol. In software terms, the processing device presents a set of possible operations through an Instruction Set Architecture (ISA). If the ISA is a description of the behaviors of the device, then the microarchitecture is the implementation of those behaviors. Advances in physics, transistor design, and device manufacturing techniques can benefit microelectronic devices of all kinds; however, microarchitecture design decisions are heavily influenced by the target market of the resultant product. While all devices strive to achieve good efficiency, balancing performance and power consumption, the application area will dictate design constraints such as size, the energy budget, and maximum power. We may group micro-architecture characteristics grouped into four areas: deeply embedded, embedded/mobile, general purpose, and servers/high-performance. These are not necessarily strict boundaries and properties often transfer between areas over time, as technology or commercial pressures permit. At present, micro-architectures have significantly different drivers for HPC/data centers, general purpose, and embedded systems/portable systems.