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Power Amplifiers and Switches
Published in Nassir H. Sabah, Electronics, 2017
P11.3.4 Given a class A direct-coupled amplifier as in Problem P11.3.3, with RE = 1 Ω, RL = 10 Ω, and VCC = 24 V. Determine ICQ, VCEQ, PS, PL(max), and ηmax. Neglecting the power dissipated in the bias network supplied from VCC and the power due to the base current, what are the maximum and minimum values of the power dissipated in the transistor?
Design of self-biased folded cascode CMOS op-amp using PSO algorithm for low-power applications
Published in International Journal of Electronics Letters, 2019
Hassan Jassim Motlak, Mohammed Jasim Mohammed
The device that has become one of the most diverse and important building blocks in analog circuit design is the operational amplifier. The operational amplifier is a high-gain direct-coupled amplifier usually include one or more differential amplifiers followed by a level transistor and output stage (Yadav, 2012; Azmi and Sunil Suresh (2014). For analog circuit design in a mixed-signal system, the complementary metal-oxide semiconductor (CMOS) technology has become dominant over bipolar technology due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip (Mishra & Nema, 2013). Several CMOS op-amps are designed in literatures (Farahmand & Shamsi, 2012; Patel & Thakker, 2016; Prajapati & Shah, 2015; Srinivas, Balaji, & Padma Sree, 2016; Vural, Erkmen, Bozkurt, & Yildirim, 2013; Vural & Yildirim, 2012) to optimise the performance parameters of CMOS op-amp. Genetic algorithm used to optimal dimensions of each transistor to improve op-amp performance for analog and mixed signal integrated circuit design (Srinivas et al., 2016). Modified particle swarm optimisation (PSO) algorithm-based optimiser for automatic circuit design. The performance of the modified PSO algorithm is compared with two other evolutionary algorithms, namely, ABC algorithm and standard PSO algorithm by designing two-stage CMOS operational amplifier (Patel & Thakker, 2016). An efficient optimization methods for sizing a differential amplifier with current mirror load. The aim is to minimise MOS transistor area using three evolutionary algorithms, differential evolution, artificial bee colony algorithm and harmony search (Vural, Erkmen, et al., 2013, Vural & Yildirim, 2012). PSO algorithm has been used for the optimum design of CMOS analog circuits with high optimisation skill in small computational time. Parameter values obtained from PSO algorithm are verified using spice circuit simulator. In this work, C code of PSO algorithm has been interfaced with Ngspice circuit simulator for circuit optimisation (Prajapati & Shah, 2015). Investigates nature-inspired met heuristics for optimised sizing of a CMOS comparator with PMOS input driver. The aim is to minimise MOS transistor area using two nature-inspired met heuristics, differential evolution and harmony search (Vural, Bozkurt, & Yildirim, 2013). A novel folded cascode operational amplifier is proposed which improves DC-gain using positive feedback technique (Farahmand & Shamsi, 2012).