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CMOS SOI Memory Design Technology
Published in Krzysztof Iniewski, Circuits at the Nanoscale, 2018
Kazutami Arimoto, Fukashi Morishita
Figure 5.15 shows the current-sense amplifier and word driver. Memory cells are connected to a negative voltage–VDD, whose voltage is supplied by the charge pump circuit via memory cell mirrors. The memory cell mirrors are arranged with the purpose of setting each read voltage of the bit line BL and the reference bit line RBL1, RBL0 at the value in the vicinity of 0 V. The write driver is driven with the supply voltage of 1/2VDD, and outputs 1/2VDD at “1”-write and 0 V at “0”-write. In addition, the write drivers leading to RBL1 and RBL0 lead to output “1” and “0” data, respectively. The sense amplifier includes a differential amplifier with two pairs of parallel inputs. The RBL1 voltage of VBL1 and the RBL0 voltage of VBL0 are input into one of the parallel inputs, and the BL voltage VBL is input as another parallel input. Because “1” and “0” data are always retrieved from RBL1 and RBL0, respectively, the relation of VBL1 > VBL0 is satisfied. In the case of “1”-read, VBL is equal to VBL1. Conversely, in the case of “0”-read, VB0 is equal to VBL0. VBL1, VBL0, and VBL are compared in the differential amplifier. The sense amplifier outputs the amplified storage data detecting this voltage difference with 4.3 ns after the WL activation.
Multiple-Valued Logic Circuits
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
In multiple-valued flash memory circuits, the floating gate of each EEPROM memory cell transistor is charged to one of the multiple values that creates one of the several memory cell transistor threshold voltages. Each memory cell transistor, when driven with the specified read gate voltage, generates one of the multiple logical drain current values. The multiple-valued drain currents are then decoded by a current sense amplifier column read circuit. The sense amplifier serves as an analog-to-digital converter that translates the multiple-valued drain current into an equivalent set of binary logical output signals with voltages compatible with the rest of the computing system. Four-valued signals are most commonly used. A few 16-valued EEPROM memory cells have been examined [13] and a 256-valued EEPROM “analog memory” has been used in a commercial analog audio storage product [14].
Random Access Memories
Published in Muzaffer A. Siddiqi, Dynamic RAM, 2017
A capacitor-less SOI DRAM cell have been given much earlier, using two transistors, but it was operationally complex and occupied larger chip area [24], whereas the aim was to get a DRAM cell in an area of 4F2. Such a simple structure, which used three signal lines and a single channel, was given [23] which used the property of body-charging effect in PD SOI MOSFET, an effect considered problematic in normal SOI MOSFET working. Utility of the concept was shown on MOSFETs at 0.25 μm and 0.13 μm SOI CMOS technology. Positive substrate charge was created through impact ionization near the drain by applying a positive drain voltage pulse, which increased the source current and it corresponded to a high. A high can also be written using source side impact ionization by negatively biasing the drain and gate. For a 0.25 μm NMOS, writing operation took 3 ns. A low state was written, again in 3 ns, through removing holes from the substrate at the source or drain side. Figure 1.13 shows the basic storage of high and low. Data stored was read by comparing the source current with that of a reference cell using a current sense amplifier. Reading was done at a low drain voltage to make it nondestructive.
Design of Virtual Inertia Controller for DC Microgrid Using Zero Placement Technique
Published in Electric Power Components and Systems, 2022
Gurunandh Vadakupattu Swaminathan, Krishnakumar R. Vasudevan, Vigna Kumaran Ramachandaramurthy, Somasundaram Periasamy
The controller in Figure 2 is designed using the proposed methodology for the hardware parameters given in Table 4. The actual HV-side voltage is sensed through a resistor divider and HV-side current required for VIC is sensed using a current sense amplifier connected across a shunt resistor. To observe the voltage response during load addition and rejection, the load connected to the system is varied. From Figure 19(a), it can be seen that the DC bus voltage is 46.4 V for an initial loading condition of 0.2 A (Figure 19(b)). When the load was increased to 0.35 A, the voltage decreased smoothly to 45.2 V. Next, Figure 20(a) shows that voltage rises smoothly back to 46.4 V from 45.2 V when the load was decreased from 0.35 A to 0.2 A (Figure 20(b)). The theoretical settling time calculated using Eq. (3) as 240 ms (=4×8×0.0075) approximately equals the experimental value (270 ms) in Figures 19(a) and 20(a). To have a benchmark response of the system without the inertia control, the traditional droop control was implemented in this experimental setup with the same parameters (Table 4) which yielded much quicker responses shown in Figures 21 and 22 for load addition and rejection, respectively. Thus it can be concluded that the proposed zero placement technique achieves a smooth voltage profile in real-time.
A manhattan metric based perturb and observe maximum power point tracking algorithm for photovoltaic systems
Published in Energy Sources, Part A: Recovery, Utilization, and Environmental Effects, 2022
A Max4080 high-side current-sense amplifier is utilized in the experimental setup to sense PV current. PV array voltage and current signals are sampled using the built-in 10-bit precision ADC of the ATmega328p. Then, these signals are smoothed out through a moving average filter. The MPO algorithm processes filtered Vpv and Ipv signals to generate duty signals. Also, the microcontroller transfers these values to the PC for later analysis.
Overcurrent protection utilising high speed and accurate current sensing circuit for switching mode DC-DC converter
Published in International Journal of Electronics Letters, 2019
Arash Abbasi, Kok Hing Lee, Boon Hean Pui, Mehran Raeisinafchi, Seng Siong Lee, Ahmed Saad
Lastly, an accurate current-sense amplifier can be achieved by combining (iii) voltage-to-current converter together with (iv) current-to-voltage converter. Equations (7) and (8) shows that the accuracy of on-chip resistors from both (iii) and (iv) due to process variation can be cancelled out by proper matching of R1 and R2 resistance values.