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Transport Phenomena in Quantum Nanostructures under an Electric Field
Published in Jyoti Prasad Banerjee, Suranjana Banerjee, Physics of Semiconductors and Nanostructures, 2019
Jyoti Prasad Banerjee, Suranjana Banerjee
The discrete nature of electrons is manifested as charge-dependent single electron transport in a very low-dimensional quantum structure like quantum dot. In macroscopic structure, the discreteness of electron transport cannot be observed in the local electron density or the current density, except the shot noise arising from the random nature of electrons entering the device structure. With continuous shrinking of dimensions of microscopic device structure, the new phenomenon of single electron transport takes place due to which the magnitude of current flowing through the device decreases continuously. In this case, the transport of one electron depends on that of other electrons due to Coulomb force acting on the electrons. Single electron transistor is a device based on single electron transport, where the discreteness of electron charge is manifested in the device transport properties. Let us consider that a single electron enters an extremely low-dimensional device like quantum dot. The dot acts like a Coulomb island whose electrostatic potential increases significantly due to the arrival of one electron. If Q is the charge and C is the capacitance of the sample, the charging energy is given by
Silicon Single-Electron Transistor
Published in Jian-Bai Xia, Duan-Yang Liu, Wei-Dong Sheng, Quantum Waveguide in Microcircuits, 2017
Jian-Bai Xia, Duan-Yang Liu, Wei-Dong Sheng
The operation principle of the single-electron transistor (SET) is to control one electron through a very small quantum dot. The performance of the SET is enhanced with the decreasing scale of the quantum dot. Therefore, the quantum dot is generally smaller than 10nm $ {\text{nm}} $ , very suitable to be high-density integrated. Meanwhile, the property of a single electron permits it to operate at ultra-low power because the power dissipated in the circuit is proportional to the number of participating electrons. SETs have a peculiar I - V characteristic, which is absent for a general MOSFET. All these properties make it possible for SETs to become high-performance circuits in a very small area.
A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications
Published in International Journal of Electronics, 2018
Mojtaba Maleknejad, Somayyeh Mohammadi, Keivan Navi, Hamid Reza Naji, Mehdi Hosseinzadeh
Feature size scaling is one of the most important criteria of improving the performance and decreasing the power-delay product (PDP) or energy consumption, of digital circuits. But the conventional metal-oxide semiconductor field effect transistor (MOSFET) technology encounters serious challenges in small nanoscale region, such as short channel effects, large parametric variations and exponential increasing in leakage current, which defer the advance towards higher performance systems (Sinha, Kumar, & Chaudhury, 2013). Therefore, other technologies have been considered such as quantum-dot cellular automata (Cho & Swartzlander, 2013), single electron transistor (Lee, Lee, Chung, & Kim, 2011), multi-gate field effect transistor (Put et al., 2007) and carbon nano tube field effect transistor (CNFET) (Appenzeller, 2008). Among nanotechnologies, CNFETs are the most promising successor to the MOSFETs for having, potentially, better performance with respect to speed, power consumption, working frequency and low-power supply voltage design (Lin, Kim, & Lombardi, 2011). Moreover, in CNFET technology, pCNFET and nCNFET have the same device geometries, motilities and current drive capacities. It is very important for transistor sizing in the complex circuits (Deng & Wong, 2006).
Test Pattern Generator for MV-Based QCA Combinational Circuit Targeting MMC Fault Models
Published in IETE Journal of Research, 2022
Some of such paradigms are Single Electron Transistor (SET) [4], Resonant Tunneling Diode (RTD) [5] and Quantum-dot Cellular Automata (QCA) [6]. Among these, QCA has attracted more attention due to the features like low power dissipation, high device density and high switching speed. QCA is an array of cells in which each cell consists of four or six quantum dots. The basic devices in the QCA are MV, inverter, binary wire, fanout wire and L-shaped wire [7]. Each QCA synthesis circuit consists of a network of MVs and inverters.
A novel efficient coplanar QCA full adder and full subtractor design
Published in International Journal of Electronics, 2023
Radhouane Laajimi, Lamjed Touil, Ali Newaz Bahar
On one hand, conventional Completely Metal Oxide Semiconductors (CMOS) technology based on transistors cannot be minimised significantly to a small size, as compared to their actual dimensions, due to problems with current leakage, which prevents the device from shutting down properly, and because of higher heat dissipation, leading to the risk of chip destruction. Thus, designers have been searching for alternative technology that provide lower energy consumption and higher density used for Arithmetic Logic Unit (ALU) applications for any computer devices. At the same time, the scalability of traditional technology is coming to an end, making it necessary to develop monomolecular devices. The International Technology Roadmap for Semiconductors (ITRS) outlines a number of new nano devices that could correctly replace CMOS technology, including the Carbon Nanotubes (CNT), Single-Electron Transistor (SET), Resonant Tunnelling Diode (RTD), single-electron, with Quantum Dot Cellular Automata (QCA; International Technology Roadmap for Semiconductors, 2011). This last technology is the fastest growing alternative for designing ultra-high density, ultra-low power, ultra-high speed digital circuits that can be reduced to the molecular nanoscale (Lent et al., 1993). This is a rapidly growing nanotechnology which has a high potential to complement and eventually replace the conventional CMOS technology (Angizi et al., 2015; Azghadi et al., 2007; Berzon & Fountain, 1999). In contrast to classical CMOS devices, QCA technology offers binary numbers that reflect electron positions within selected quantum dots. As a result, the QCA design has better performance than CMOS regarding switching speed, device density, and power consumption. In fact, the QCA technology provides complete and fully efficient power dissipation advantages. Moreover, this technology can reach an important switching speed of 10 ps, a high density of 1012 devices/cm2 and a low power dissipation of 100 W/cm2 (Walus et al., 2003). The digital QCA circuit design is exploited for practical uses in the design of low-power devices. One of the most used operations in QCA digital is the Full Adder-Subtractor used in many logic applications including division, subtraction, addition and multiplication (PZ Ahmad et al., 2017; Cho & Swartzlander, 2009). Recently, many researchers have suggested the implementation of adders and Subtractors circuit by using QCA technology. The majority of these conceptions are based on an approach known as gate-based design. For this reason, this approach depends on the utilisation of a majority voter that can operate with large complex circuit designs, and high power consumption. Thus, an optimal Full Adder-Subtractor (FAS) design based on QCA technology allows to design arithmetic logic circuits used for computing.