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Models and Tools for Complex Embedded Software and Systems
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
Ideally, these three (sets of) models should be constructed and relationships among their elements should be defined in such a way that the following applies: The platform model abstracts the platform properties of interest for evaluating the mapping solution with respect to quantitative properties that relate to performance (time), reliability, cost, extensibility, and power (and possibly others).The platform model permits verifying the existence of a mapping solution that provably preserves the semantics properties of interest of the functional model. This property is of particular interest when formal safety properties are demonstrated on the functional model. In order for these properties to carry over to the implementation, a formal proof of correctness must be provided.The implementation model complies with the programming and implementation standards in use and allows the analysis of the properties of interest. An example of such analysis is schedulability analysis that refers to the capability of a multiprogrammed system to meet timing constraints or deadlines.
Scheduling Analysis and Interrupt Handling
Published in Gedare Bloom, Joel Sherrill, Tingting Hu, Ivan Cibrario Bertolotti, Real-Time Systems Development with RTEMS and Multicore Processors, 2020
Gedare Bloom, Joel Sherrill, Tingting Hu, Ivan Cibrario Bertolotti
This chapter introduced a couple of popular schedulability analysis techniques, namely utilization-based tests and response time analysis (RTA). In the case of response time analysis, it was also shown how to refine and extend the analysis, starting from a basic periodic task model and then going towards a more complex model that incorporates task interactions, self-suspension, and interrupt handling.
Networked Embedded Systems: An Overview
Published in Richard Zurawski, Networked Embedded Systems, 2017
Design methods for networked embedded systems fall into the general category of system-level design. They include three aspects, namely, node design (covered extensively in Section I of the book), network architecture design, and timing analysis of the whole system. The network architecture design involves a number of activities. One of them is selection of an appropriate communication protocol and communication medium. A safety-critical application will employ a protocol based on Time Division Multiple Access (TDMA) medium access control to ensure deterministic access to the medium. For an application in building automation and control, the choice of the communication medium may be the power line wires in the existing building or dedicated twisted pair wires in a new construction. The topology of the network heavily depends on the application area. In industrial automated systems, the prevalent topology is the bus. Building network may have a complex topology with many logical domains. Configuration of the communication protocol, among other things, involves allocation to the communication nodes priorities in the priority busses, or slots in the TDMA-based protocols, for instance. The timing analysis aims at obtaining actual times for the chosen architecture. That involves task execution time measures such as worst-case execution time (WCET), best-case execution time (BCET), and average execution time; response time of a task from invocation to completion; end-to-end delay; and jitter, or variation in execution time of a task, for instance. In the end, the whole system has to be schedulable to guarantee that deadlines of all distributed tasks communicating over the network will be met in all operational conditions the system is anticipated to be subjected to. As an example, let us consider a simple control loop comprising a sensing node with a single application task dedicated to sensing, an actuator node processing data received from the sensing node, and generating control value delivered to an actuator over a dedicated link. The composite time of data processing (WCET) and transmission (worst-case response time) has to be shorter or equal to the maximum time allowed by the process dynamics under control. In case of other nodes connected to the shared communication network and forming similar control loops, a contention for the medium access may arise to be remedied for safety-critical and hard real-time systems by adopting a fixed transmission schedule as in the case of the time-triggered TDMA-based protocols, for instance. The schedulability analysis is to determine if the worst-case response time for all those composite tasks forming control loops is less then or equal to the deadline.
mcDVFS: cycle conserving DVFS scheduler for multi-core mixed criticality systems
Published in International Journal of Parallel, Emergent and Distributed Systems, 2023
Louella Colaco, Prashiksha Jain, Arun S. Nair, Biju K. Raveendran, Sasikumar Punnekkat
When the functioning of a system requires not only logical accuracy but also timing accuracy of the actions executed, the system is said to be real-time [1]. For instance, in avionic/automotive applications, engine management and navigation/ gearbox control systems are subject to strict timing restrictions that come from the software/hardware systems they govern. To ensure timing guarantees while maximizing the use of the processing power at hand, appropriate scheduling strategies backed by precise schedulability analysis methods are a mandatory requirement [1]. Additionally, these methods must be able to examine an application's worst-case behaviour and provide evidence that time restrictions will be met under all circumstances subject to assumptions regarding the application's behaviour, scheduling policies, etc.