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Probability and Statistics
Published in Jerry C. Whitaker, Electronic Systems Maintenance Handbook, 2017
Devices can exhibit different faulty behavior, some of them malicious. The most famous is the lying clock problem, which can occur in system synchronization when correcting for clock drift. Clock A is good, but slow, and sends 11 am to the other two clocks.Clock B is good, but fast, and sends 1 pm to the other two clocks.Clock C is faulty. It sends 6 am to clock A and 6 pm to clock B.Clock A averages the three times and resets itself to 10 am.Clock B averages the three times and resets itself to 2 pm.
WirelessHART, The Leading Technology for Industrial Wireless Networked Control Systems
Published in Tran Duc Chung, Rosdiazli Ibrahim, Vijanth Sagayan Asirvadam, Nordin Saad, Sabo Miya Hassan, TM, 2017
Tran Duc Chung, Rosdiazli Ibrahim, Vijanth Sagayan Asirvadam, Nordin Saad, Sabo Miya Hassan
Some main causes of delay in the WNCS are (i) node joining time [18]; (ii) clock drift [62]; and (iii) individual device internal processes [91]. The join time of a wireless node strongly depends on the number of nodes in the network. In general, a network with a single node takes less time for the node to join the network. While a network with multiple nodes takes longer for network formation or for all nodes to join the network. On the other hand, the clock drift is the result of the time difference in network devices’ internal clocks; it can be solved by network-wide synchronization [96]. For Linear Technology SmartMesh WirelessHART nodes, the achievable clock accuracy is less than 1 ms [97]. Some important devices in the network are the controller, gateway, plant’s sensor, and actuator. Their internal processes contribute mainly to the delay of the network. Wireless delay can be measured accurately by the gateway as it is able to read timestamps of any message in the network. While wired delay can be lumped together with process delay as process dead-time.
Self-Localization
Published in Prabhakar S. Naidu, Distributed Sensor Arrays Localization, 2017
where δ is clock drift, dγfalse(tfalse)/dt=1+δ, and µ is clock offset (several µs). Clock drift affects the time interval measurement. If a single sensor wants to measure a time interval τ = t2 − t1 sec, then the estimated time interval is
A bi-Level programming method for SPaT estimation at fixed-time controlled intersections using license plate recognition data
Published in Transportmetrica B: Transport Dynamics, 2023
Jiarong Yao, Hao Wu, Keshuang Tang
Time-dependent fixed-time control still prevails in most Asian countries, including China, Japan, India, Korea, and Turkey (Koukoumidis, Peh, and Martonosi 2011). During a time-of-day (TOD) period, the signal timing data for a fixed-time intersection generally remain unchanged, resulting in periodic vehicle stop-go variation patterns. For fixed-time signalized intersections, signal phase and timing (SPaT) information consists of the cycle length, the phase structure, the length of each phase, and the offset (starting point) of each phase. With SPaT information, most performance measures such as traffic volume, queue length and delay can be obtained given the detected traffic demand (Skabardonis and Geroliminis 2005; Liu and Ma 2009; Hao, Ban, and Yu 2014). In addition to performance evaluation, the current signal scheme is always used as a reference for fine tuning or optimization of timing parameters, like cycle length, offset and split. Thus, obtaining an accurate and reliable SPaT is essential for traffic operation evaluation and optimization. However, accurate signal timing data are difficult to obtain due to the clock drift of the signal control system. Because the signal timing data and detection data are transmitted through different communication systems and channels, the asynchronization between them may create a communication time lag or data error, in some way analogous to clock shew or clock jitter, thus causing a mismatch when using multi-source data are for traffic operation evaluation.