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Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
Laurent Maillet-Contoz, Jérôme Cornet, Alain Clouard, Eric Paire, Antoine Perrin, Jean-Philippe Strassen
In this section, we give an overview of the importance of standards in the system-level design area. It is possible to categorize the various types of standards as follows: Design and modeling language standards, such as VHDL/Verilog/SystemVerilog and SystemC: From an industrial perspective, they are important in order to ensure model usability over a multiyear period and to secure corresponding investments.Methodology standard: UVM [10] is emerging as a recognized standard to rationalize the structure of RTL verification environments and ease reuse and sharing of verification platforms.Interoperability standards, which we describe in more detail later on in this section: One can list model-to-model interoperability standards like SystemC/TLM [13], as well as model-to-tool interoperability standards like APIs for transaction recording as defined in the SystemC Verification Library [14] or parameter definitions as defined in the upcoming cci_param standard [15].
Digital IC Design for Transceiver SOC
Published in Kaixue Ma, Kiat Seng Yeo, Low-Power Wireless Communication Circuits and Systems, 2018
Wang Yisheng, Kaixue Ma, Kiat Seng Yeo
The Universal Verification Methodology (UVM) is a standardized methodology for verifying IC design [6]. It is an open-source SystemVerilog library allowing the creation of flexible reusable verification components and assembling the test platform using directed and constrained random test bench generation, coverage-driven verification, and assertion-based verification methodologies. It is very important and widely used to improve test bench reuse and make verification code more portable in the SOC verification flow.
Functional verification of a sigma-delta ADC real number model
Published in International Journal of Electronics, 2022
Nikolaos Georgoulopoulos, Prof. Alkis Hatzopoulos
UVM is an IEEE methodology standard (IEEE 1800.2–2017) for IC designs verification boosted by SystemVerilog, having as goal to create verification components for transaction-level modelling (TLM) for more efficient communication between the components (Accellera, 2015). A base class library forms its spinal cord, making it suitable for constructing Universal Verification Components (UVCs). UVC is basically a concept of the stimuli generation, checking, monitoring and coverage gathering mechanisms for design, protocol, module verification, etc. Furthermore, depending on the design under test (DUT), a UVC can consist of one or more agents where each agent can connect via a specific interface to the DUT for verifying whole or part of its functionality.