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An Impact of Aging on Arbiter Physical Unclonable Functions
Published in Durgesh Nandan, Basant K. Mohanty, Sanjeev Kumar, Rajeev Kumar Arya, VLSI Architecture for Signal, Speech, and Image Processing, 2023
Kurra Anil Kumar, Rani Nelakuditi
In a real time scenario, the amount of process variations that occurred at each and every stage can be modeled by using statistical static timing analysis (SSTA). In the same way, the amount of delay variations can be approximated by using the Gaussian distribution. Based on the above discussions we can model each multiplexer as an independent random variable Di, represented by the Gaussian random variable such as N(µ, σ2), where µ represents the mean and σ2 indicates the standard deviation of delay of the mux. The delay difference between top and bottom MUXes can be represented by Δi = Dit − Dib ~ N(0,2σ2) . the final response obtained from the last stage can be modeled by RN=∑i=1N(−1)Ci′Δi where Ci′ = ϕNj=i+1Cj and c′N = 0. The final response generated from the final stage can be given by R = sign(RN) = 1 if Rn is greater than 0 else output is 0, respectively.
Design by Optimization
Published in Wai-Kai Chen, Computer Aided Design and Design Automation, 2018
In the presence of statistical variations, it is important to perform timing optimization based on statistical static timing analysis. An obvious way to increase the timing yield of a digital circuit is to pad the specifications to make the circuit robust to variations, i.e., choose a delay specification of the circuit that is tighter than the required delay. This new specification must be appropriately selected to avoid large area or power overheads due to excessively conservative padding.
Artificial neural network model for arrival time computation in gate level circuits
Published in Automatika, 2019
There are two engines for timing analysis, namely, the static timing analysis (STA) engine and the statistical static timing analysis (SSTA) engine. STA is a method that validates the timing of a circuit without using an input test vector, and the whole circuit need not be simulated. It is implemented such that it is input-independent and finds the extreme or worst-case delay of the circuit by considering all possible input combinations. The delay computation and timing metrics can be obtained by circuit simulation. It is a very time-consuming process and the results are based on theoretical assumptions. There is always a trade-off between speed and accuracy in STA. Technological advances in the nanometre regime lead to many parametric variations. Control of the process parameters is very important and increasingly difficult. Process parameters are random in nature. To account for these process parameters, SSTA is preferred. The objective of SSTA is to improve the accuracy without much trade-offs in speed, by considering most of the process variables.