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Wavelet VLSI Architectures
Published in Keshab K. Parhi, Takao Nishitani, Digital Signal Processing for Multimedia Systems, 2018
Tracy C. Denk, Keshab K. Parhi
Retiming is a technique used to change the locations of registers in a circuit without affecting the input/output characteristics of the circuit. To retime the architecture in Fig. 13.10, we can simply examine all connections between two adjacent processing elements (PEs) and remove one delay from each connection which goes from right-to-left and add one delay to each connection which goes from left-to-right. This technique is known as cutset retiming. For example, consider the connections between PE1 and PE2 in Fig. 13.10. Starting from the top of the figure, there are six connections which contain 4, 2, 1, 0, 0, and 0 sample delays. If we remove one delay from each connection which goes from right-to-left and add one delay to each connection which goes from left-to-right, then the connections contain 4 – 1 = 3, 2 – 1 = 1, 1 – 1 = 0, 0 + 1 = 1, 0 + 1 = 1, and 0 + 1 = 1 delays. Performing cutset retiming on all connections between each adjacent pair of PEs in Fig. 13.10 results in the architecture shown in Fig. 13.11.
Power Analysis and Optimization from Circuit to Register-Transfer Levels
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Jose Monteiro, Rakesh Patel, Vivek Tiwari
Retiming was first proposed as a technique to improve throughput by moving the registers in a circuit while maintaining input–output functionality. The use of retiming to minimize switching activity is based on the observation that the register outputs have significantly fewer transitions than the register inputs. In particular, no glitching is present. Moving registers across nodes through retiming may change the switching activity at several nodes in the circuit. In the circuit of Figure 3.8(a), the switched capacitance is given by N0CB + NlCFF + N2CC and the switched capacitance in its retimed version, shown in Figure 3.8(b), is N0CFF + N4CB + N5CC. One of these two circuits may have significantly less switched capacitance. Heuristics to place registers such that nodes driving large capacitances have reduced switching activity with a given throughput constraint have been proposed [21].
VLSI architecture design fundamentals
Published in Zhang Xinmiao, VLSI Architectures for Modern Error-Correcting Codes, 2017
Retiming is a technique that is used to change the locations of delay elements in a circuit without changing the overall function. It can be applied to any cutset, and is not limited to feed-forward cutsets. Pipelining can be considered as a special case of retiming. Let G1 and G2 be the two disjointed subgraphs resulted from removing the edges in a cutset. In a retiming solution, k delay elements can be removed from each edge going from G1 to G2 if k delay elements are added to each edge from G2 to G1. It should be noted that the number of delay elements on any edge should be non-negative before and after retiming.
The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals
Published in Automatika, 2023
Kalamani C., Kamatchi S., Sasikala S., Murali L.
The DFG should not have a negative value to achieve proper folding. The negative delays on some edge are noted so retiming for folding is performed. The location of delay elements in the circuits is changed using the Retiming transformation technique. A special case of retiming known as Cut set [13,14] retiming is used in the design. DFG with the cut set is specified in Figure 7. The DFG after retiming is revealed in Figure 8.