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Packet Security
Published in Heqing Zhu, Data Plane Development Kit (DPDK), 2020
In 2010, Intel® released AES New Instructions (AES-NI) in the “Westmere” processor. Since then, AES-NI has been available on the x86 processor. There are six instructions that offer full hardware support for AES. Four instructions support the AES encryption and decryption, and two instructions support the AES key expansion. AES-like cryptographic algorithms use the repeated operations for multiple data blocks. This suits well to single instruction, multiple data (SIMD) to process multiple data blocks in one operation. In today’s mainstream Xeon server, AES-GCM is able to achieve 0.64 cycles per byte. For the next-generation server (Ice Lake), it introduced the additional vector AES instructions, and it is possible to push the performance limit to 0.16 cycles per byte, https://eprint.iacr.org/2018/392.pdf.
Solving mixed-integer nonlinear programmes using adaptively refined mixed-integer linear programmes
Published in Optimization Methods and Software, 2020
Robert Burlacu, Björn Geißler, Lars Schewe
All instances are solved using the C++ software framework LaMaTTO++, see [23], on a cluster using 12 cores of a machine with two Xeon 5650 ”Westmere” chips (12 cores + SMT) running at 2.66 GHz with 12 MB Shared Cache per chip and 24 GB of RAM. Furthermore, we utilize Gurobi (version 6.0.4) as MIP solver [17], using the 12 cores mentioned above for the parallel solving of each MIP. As stated above, Baron and SCIP are used as state-of-the-art MINLP solvers, and CONOPT3, which in our case performs better than CONOPT4, as local NLP solver, all within GAMS (version 24.8.3); see [4]. Note that for a fair comparison, Baron and SCIP also have 12 cores available and run in parallel. In addition, Baron and SCIP are given the same reformulations of the nonlinear constraints as described in Section 5.
Efficient numerical solution of micro–macro models for multicomponent transport and reaction problems in porous media
Published in Applicable Analysis, 2022
The time needed for phase solve 2 is exactly the time that is consumed by linear solvers in a Newton's method for a one-scale problem (assuming that the number of iterations is equal). Table 2 shows the computation time for one time step of time step size 0.1 s(four iterations) for different numbers of processors. We see that the computational overhead arising from the multiscale nature seems to scale perfectly. For the computation we used Xeon 5650 ‘Westmere’ chips (12 cores + SMT) at 2.66 GHz with 12 MB Shared Cache per chip and 24 GB of RAM (DDR3-1333). SMT was used, i.e. we used two processes per physical CPU.