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Exceptions, interrupts, and input/output systems
Published in Joseph D. Dumas, Computer Architecture, 2016
Processors that are intended for use in embedded systems (inside some other piece of equipment) also generally have an alternate reset mechanism known as a watchdog timer. (Some manufacturers have proprietary names, such as computer operating properly [COP], for this type of mechanism.) A watchdog timer is a counter that runs continuously, usually driven by the system clock or some signal derived from it. Periodically, the software running on the CPU is responsible for reinitializing the watchdog timer to its original value. (The initial value chosen and the frequency of the count pulses determine the timeout period.) As long as the timer is reinitialized before going through its full count range, the system operates as normal. However, if the watchdog timer ever rolls over its maximum count (or reaches zero, depending on whether it is an up or down counter), it can be assumed that somehow the system software has locked up and must be restarted. A hardware circuit detects the timer rollover and generates a system reset. This type of monitoring mechanism is often necessary in embedded systems because it may be inconvenient or impossible for a user to manually reset the system when trouble occurs. Not all computers are desktop workstations with convenient reset buttons. The processor may be buried deep within an automobile transmission or, worse, an interstellar space probe.
Transport/Monitoring
Published in Paul J. Fortier, Handbook of Local Area Network Software, 1991
Timing intervals provide a relatively inexpensive means to check the operations of a device or software. If the item of interest includes timing as a critical aspect of its operation, we could use this as a test point. If the timing constraint is missed, we signal that an error condition has occurred. Such checks are best used to indicate remote failures in LANs. For example, if a message is sent, and after some specified maximum time interval no response is received, then one can assume either the media, interface units, or the remote site has failed in some fashion. Using these potential conditions the sender can perform further tests to better isolate a problem, as will be seen in the next section of this chapter. Software timers can be used as checks of overall health. The monitored software is required on each of its operations loops to get a “watchdog” timer; if the timer is not set, it is assumed the software has failed. If it is set, all goes on.
MSP432 32-bit timers and watchdog timer
Published in Ying Bai, Microcontroller Engineering with MSP432, 2016
The Watchdog timer interrupt is handled through the enable/set/clear/pending flag of the NVIC IRQ that the WDT is mapped to. When working in the Watchdog timer mode, a system reset will be generated as the time interval expires. This kind of reset can be considered as either hardware or software reset in the MSP432P401R MCU system, and it can be identified and handled by the reset controller registers. The MSP432P401R MCU supports up to 16 Hard Reset (HR) and Soft Reset (SR) sources. The reset source number of the WDT_A time-out is 1 for both HR and SR in this MCU system.
An efficient industry 4.0 architecture for energy conservation using an automatic machine monitor and control in the foundry
Published in Automatika, 2022
M. Dinesh, C. Arvind, K. Srihari
The internal timer can be affected by runaway code. An external watchdog is equipped with a separate clock source to better its reliability; if properly configured, it cannot be bypassed or disabled by runaway code. In the proposed design, the MAX705 IC is used for a hardware watchdog timer to generate a reset pulse when the supply voltage drops. Watchdog output goes low if the watchdog input for the microcontroller pin has not been toggled within 1.6 s. When it stops, the MAX705 trigger output is toggled to the controller restart pin. Also, the manual-reset input allows resetting the trigger using a push-button switch. The pin configuration of the MAX705 watchdog timer is shown in Figure 5.