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Petri Net Modeling and Scheduling of Automated Manufacturing Systems
Published in Cornelius Leondes, Optimization Methods for Manufacturing, 2019
MengChu Zhou, Huanxin Henry Xiong
There are four main stages in a typical Integrated Circuit (IC) manufacturing process: wafer fabrication, wafer sort, assembly cycle, and final test (2). The first stage of IC production is called wafer fabrication. In wafer fabrication, the integrated circuits are manufactured on a silicon or gallium arsenide wafer using photolithography, etching, diffusion, and ion implantation processes. In the next stage, wafer sort, the individual circuits (dice) on a wafer are tested for functionality by means of electrical probes. Dice that fail to meet specifications are marked with an ink dot. The wafer then goes to assembly cycle, where the wafer is sawed; the defective dice are discarded; the good dice are bounded to the lead frames; the wires are bounded and then encapsulations are followed. After the assembly cycle, each IC ship is subjected to final tests to determine whether or not it is operating at the required specifications (Lee et al. 1992 [10]).
ESD Development in Foundry Processes
Published in Juin J. Liou, Krzysztof Iniewski, Electrostatic Discharge Protection, 2017
It is very costly for a manufacturer to own and operate the wafer fabrication, assembly, and test facilities. The start-up cost for each of these facilities is high, and they need to be running at near capacity to be cost-effective. Most IC suppliers cannot afford to do this. This is especially true for wafer fabrication. As a result, many IC manufacturers use outside wafer fabrication services (foundries) to build their products. This choice can complicate the development of a new product. The focus of this chapter is to detail the process used to implement a new IC design in a foundry process and also highlight the challenges with respect to ESD design.
Dynamic analysis and design of a semiconductor supply chain: a control engineering approach
Published in International Journal of Production Research, 2018
Junyi Lin, Virginia L.M. Spiegler, M.M. Naim
Specifically, there are two main manufacturing stages for microprocessor chip production from a material flow perspective: fabrication and assembly. The polished disc-shaped silicon substrates (wafers) as inputs are taken into a wafer fabrication facility, and through several complicated sequences to produce fabricated wafers (composed of integrated circuits, i.e. ICs or dies). A vertical cross-section of an integrated circuit reveals several layers formed during the fabrication process. Lower layers include the critical electrical components (e.g. transistors, capacitors), which are produced at the ‘front-end’ of the fabrication process. Upper layers, produced at the ‘back-end’ of the fabrication process, connect the electrical components to form circuits. In the second assembly phase, the fabricated wafers are cut into dies and stored in the ADI warehouse to wait for the assembly process. After passing assembly and test plants to ensure operability, the finished microprocessors are stored in the FGI for customer orders. A three-stage supply chain, including fabrication, assembly and distribution, is thereby created to represent the manufacturing process.
A discrete spatial model for wafer yield prediction
Published in Quality Engineering, 2018
Hao Wang, Bo Li, Seung Hoon Tong, In-Kap Chang, Kaibo Wang
The occurrence of noncomforming chips directly affects the yield of a process, which is critical for production productivity, material planning and quality control. Accurate yield prediction is always appealing for proper production planning and control (Joseph and Adya 2002). In wafer fabrication, yield is commonly defined as the proportion of the total number of chips that are successfully produced. Many researchers have proposed different yield models for process characterization and other purposes. In general, yield losses can be regarded as the product of four components: the wafer process yield Ywp, referring to the percentage of wafers arriving at the wafer probe step; the wafer probe yield Ycp, referring to the percentage that pass the probe step; the assembly yield Yap, associated with the assembly process; and the final test yield Yft, referring to the percentage that survive through the final electrical test (Kuo and Kim 1999). Figure 2 summarizes these four yield losses in a flow chart.
Detection and clustering of mixed-type defect patterns in wafer bin maps
Published in IISE Transactions, 2018
Jinho Kim, Youngmin Lee, Heeyoung Kim
The wafer fabrication process consists of multiple sequential processes including oxidation, photolithography, etching, ion implantation, and metallization. After wafer fabrication, a verification test, which is called wafer testing, is performed on each die (or chip) of a wafer using test equipment called a wafer prober to detect any process change and to verify whether all dies meet the product specifications. Wafer testing consists of many test items that measure the performance of the operations of required die functions in order to ensure that only good dies are sent to the next manufacturing stage. In this article, it is assumed that each die is assigned a binary value that depends on the test results for simplicity; for example, a good die is assigned a value of one, whereas a defective die is assigned a value of zero, although in practice a defective die can be further categorized based on its specific defect type (e.g., refresh, disturb failures). The resulting spatial map of a wafer, which shows the assigned binary value of each die, is called a Wafer Bin Map (WBM).