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Epitaxy
Published in Kumar Shubham, Ankaj Gupta, Integrated Circuit Fabrication, 2021
SOS involves the epitaxial growing thin layer of silicon on insulating substrate of sapphire (Al2O3) at high temperature as shown in figure 2.24. This growth is labeled ‘hetero-epitaxy’, as the grown material layer is different from that of the base material or substrate. Nonetheless, the materials and equipment utilized for the hetero-epitaxial growth of SOS are basically identical to those used in homo-epitaxial growth. Its main advantage for electronic circuits is the highly insulating sapphire substrate that provide very low parasitic capacitance, hence increased speed, lower power consumption, better linearity and more isolation than bulk silicon.
Smart structures and materials
Published in Jun Ohta, Smart CMOS Image Sensors and Applications, 2020
Silicon-on-sapphire (SOS) is a technology using sapphire as a substrate instead of silicon [249, 250]. A thin silicon layer is directly formed on a sapphire substrate. It is noted that the top silicon layer is neither poly- nor amorphous silicon but a single crystal of silicon, and thus the physical properties, such as mobility, are almost the same as in an ordinary Si-MOSFET. Sapphire is Al2O3. It is transparent in the visible wavelength region and hence image sensors using SOS technology can be used as backside illumination sensors without any thinning process [214, 245, 251, 252]; however, some polishing is required to make the back surface flat. Lateral PTrs were used in Ref. [245], while a PFM photo-sensor is used in the work of Ref. [214, 251] due to the low photo-sensitivity in a thin detection layer. Figure 3.21 shows an image sensor fabricated by SOS CMOS technology. The chip is placed on a sheet of printed paper and the printed pattern on the paper can be seen through the transparent substrate.
Selection and Use of Silicon Devices at High Temperatures
Published in F. Patrick McCluskey, Richard Grzybowski, Thomas Podlesak, High Temperature Electronics, 2018
F. Patrick McCluskey, Richard Grzybowski, Thomas Podlesak
A number of methods can provide the dielectric isolation to form SOI wafers. The earliest work on SOI circuits was performed in the 1970s with silicon-on-sapphire (SOS) devices, in which an epitaxial layer of silicon is grown on a single-crystal sapphire (Al2O3) substrate. The two materials are not particularly compatible because the crystallographic lattice spacing is very different. SOS circuits were useful for military and radiation applications, but widespread application was limited by the cost of the sapphire substrate and the relatively high level of defect density in the upper silicon material. The defect levels impacted the yield and performance of large, complex integrated circuits.
Review of Approaches for Radiation Hardened Combinational Logic in CMOS Silicon Technology
Published in IETE Technical Review, 2018
Vaibhav Sharma, Arvind Rajawat
In this paper, approaches have been classified according to their usage in radiation hardening and then discussed. In the category for modeling-based approach, a new modeling for injected current due to particle hit which is dual double exponential current source is specified for its causes and benefits. However, dual exponential current source model is a very old approach and is still used by authors. In the category for mitigation-based approaches, we have discussed briefly some of device level techniques. A new device level design requires knowledge of backend physics and is a costly process, but they remain successful with lower PAD overheads. Technologies such as silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) show better performance and hardening compared to bulk silicon. Design overheads may be reduced if two dimensional devices made of Carbon nanotechnology and graphene is used. Although, applications belonging to these materials at present are in developing stage. Gate and logic level approaches are based on circuit design modification and implemented using an algorithmic method. Since these techniques do not involve process variations hence they are widely adopted by authors. In the technique for NMI [16] of NMOSFET, a customized design for standard cells can be done with the help of a mathematical modeling if we know the change in the threshold voltage of n-channel device, i.e., ΔVtn. This technique is generalized irrespective of technology. The technique based on CVSL has an advantage of having lower PAD overhead for multi input logic as compared to static logic in condition to total dose response of n-channel devices. Further scope in CVSL is that the pull-up time, i.e., time required for output to become high from low can be lowered by effectively sizing cross coupled p-channel transistors. RADJAM does not manifest with a mathematical modeling, but in particular has a constant overload, regardless of implemented logic gate. Furthermore, a standard DTMOS inverter described in [20] has its n- and p-channel MOSFET substrates connected to its inputs. Hence, it is a candidate for better PAD performance but for a reduced critical charge tolerance. It mitigates SET, soft delay effects when combined with sizing technique. In case of logic level approaches TMR and DMR may prove redundant unless any modified voter circuit is used to reduce PAD overheads, else Table 1 can be approached for a suitable technique. Finally, in the category for testing or estimation of soft errors, approaches adopted for SET detection and SER calculation are discussed.