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Design Closure
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
The purpose of the logic/placement refinement phase is to apply placement, timing and congestion aware transformations to the logic to correct performance and power problems left over from the placement phase. The timing-driven flow outlined in the placement phase is excellent at localizing large numbers of gates to solve general performance and routability problems. However, upon the exit from that phase, there are performance-critical paths that need to be fixed individually. In addition, local power and routability issues are considered while making these optimizations. This phase has two steps. First, electrical problems such as slew limit exceptions at signal sink pins and capacitance limit exceptions at output pins are corrected. These problems are fixed by gate sizing, buffering of large fan-out nets, and repeater insertion. Second, the design is timed and optimized using the slack-take-down approach.
Advanced Research in On-Chip Optical Interconnects
Published in Christian Piguet, Low-Power CMOS Circuits, 2018
Ian O′Connor, Frédéric Gaffiot
In the case of global links, Sakurai’s formula shows that the delay time in the line becomes predominant. To limit the delay time in the metallic line, global links are routed on the upper metal layers where it is possible to increase the width and the thickness of the line, and thus to reduce the lineic resistance. Reverse scaling (by reducing the thickness of the metal layer less than the scale factor) is commonplace, leading to high aspect ratios. Gate sizing makes it possible to minimize td, and it is possible to show that td varies with lw2. This increase of the delay time with the second power of the line length cannot be avoided. Repeater insertion makes it possible to make the delay vary with lw, but this of course comes at the cost of a very large number of repeaters. In this scenario therefore, a relatively high percentage of silicon real estate and IC power consumption is devoted to interconnect instead of to data processing functions.
Generalized Buffer Insertion
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
Early work on repeater insertion focused mainly on improving interconnect timing performance. The most influential work is van Ginneken’s dynamic programming algorithm [1]. The algorithm performs buffer insertion on a fixed and embedded tree (e.g., as given by a global router) and produces an optimal timing solution under Elmore delay model [2]. Various generalizations of van Ginneken’s algorithm have appeared in the literature taking into account issues of practical importance such as buffer libraries with inverting and noninverting buffers, simultaneous wire sizing, and slew-based delay models. Additionally, generalizations that address natural constrained optimization variants of the problem (e.g., minimization of area or power consumption subject to timing constraints) have also appeared. Progress has also been made in improving computational complexity as well as practical runtime. Many of these results are presented in Chapter 26.
Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic
Published in IETE Journal of Research, 2023
V. Sulochana, C. Venkataiah, Sunil Agrawal, Balwinder Singh
In recent times, the semiconductor industry has developed more functionality for silicon on chip due to the smaller device dimensions. As the number of devices is increased on silicon chip, the connections between them also increase. As a result, the spacing between interconnects is reduced that leads to an increase in coupling capacitance. The coupling capacitance affects the signal integrity in integrated circuit that causes the crosstalk-induced delay and noise. To reduce these non-ideal effects in the binary logic system, some techniques have been introduced, such as increasing spacing between interconnects, repeater insertion, and shielding, etc [24]. The most effective way to reduce the crosstalk is active shielding. The cross sectional view of an active shielded MWCNT bundle interconnect structure and the corresponding electrical equivalent model are presented in Figures 1 and 2, respectively. In this structure, the central MWCNT bundle is treated as the victim line and the peripheral MWCNT bundles are used as the shielded lines. In order to reduce the coupling capacitance, the peripheral shielded lines should be in phase with respect to the victim line.
Novel Subthreshold Modelling of Advanced On-Chip Graphene Interconnect Using Numerical Method Analysis
Published in IETE Journal of Research, 2021
Nikita R. Patel, Yash Agrawal, Rutu Parekh
As device density in ICs increases, power dissipation has increased tremendously [9]. Further, portable e-gadgets demand low power techniques for high-end performance. In compact and portable e-systems, demand for ultra-low power has become very high. The subthreshold region of operation is one of the most efficient techniques to attain low power in circuits and systems. For ultra-low power applications, performance analysis of interconnect in the subthreshold region has been performed in [10]. To attain high performance, repeater insertion method along with the subthreshold region has been investigated. Analytical modelling of copper interconnect in the subthreshold region of operation has been formulated in [11]. In this paper, various crosstalk effects in copper interconnect operating at the subthreshold region are analysed. The subthreshold region of operation with copper interconnects has been analysed by many researchers [10,11]. However, these have been very scarcely explored for graphene interconnects. Incorporating graphene as on-chip wire together with the operating entire system at the subthreshold region is a potential and viable solution for advanced and futuristic low power applications. Consequently, this has been innovatively taken up and systematically presented in this work.
Transmission Gate as Buffer for Carbon-Nanotube-Based VLSI Interconnects
Published in IETE Journal of Research, 2018
Transmission gates (TGs) are well known for their applications in analogue switches, signal isolators, and logic circuits in microelectronic chips [1]. Their unique properties like immunity to input noise, good output swing, and less power dissipation make them ideal for low-power applications, especially as buffers in VLSI interconnects. Recent work shows low-power buffer design using four TGs inserted in an inverter circuit [2]. A new method is developed to calculate the repeater size and interconnect length to minimize the total interconnect power dissipation using CMOS inverter as repeater [3]. A smart driver using TGs has been preferred for repeater insertion [4]. The insertion of repeaters for three types of interconnects was compared by considering the impact of contact resistance [5]. Other than this, TGs have not got attention as buffers or repeaters in carbon nanotube (CNT)-based VLSI circuits, till date. CNT-based interconnects have gained prominence as the next-generation VLSI interconnects [6].