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Electromagnetic Compatibility for High-Speed Circuits
Published in Xing-Chang Wei, Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging, 2017
The 3D integration consists of 3D IC packaging, 3D IC integration, and 3D silicon integration [9]. Among all those 3D integrations, TSV-based interposer (passive and active) is preferred by industries due to its easy fabrication and good heat dissipation. Figure 1.6 shows a typical TSV-based interposer. The interposer is a silicon substrate inserted between the die stack and the second-level package. It serves as a space transformer through redistribution by connecting the fine-pitch microbumps to the coarser-pitch C4 bumps [1]. Redistribution layer (RDL) is the metal layer on the top and bottom of the interposer. It is used for the horizontal interconnection, and TSV is used for the vertical interconnection.
Cu metallisation on glass substrate with through glass via using wet plating process
Published in Transactions of the IMF, 2021
M. Takayama, K. Inoue, H. Honma, M. Watanabe
With the advent of the IoT (Internet of Things) era, enormous amounts of data are being successively accumulated through network connections. The range of application of large amount of data is being widened, and it will significantly change our lives and societies. Research and development of large-capacity and high-speed data communication technology as well as various sensors is being conducted as these comprise critical technology to realise new societies. Also, remarkable progress is being seen in new materials and nano-processing technology. In the field of electronics, finer patterning and higher integration are further promoted and high-performance circuit boards are required. Even greater insulating materials properties improvements and electronic device performances are being sought.1 The development of circuit boards using silicon for semiconductors is being pursued. In recent years, through silicon via (TSV)2 that has vias formed in silicon has been developed. Advances in semiconductor technology have made it possible to improve the degree of integration; for example, vertically stacking chips on a TSV substrate enabled the change from planar integration to three-dimensional integration of large scale integration (LSI). Accordingly, advanced packaging methods are being developed including 3D/2.5D packaging,3 Fan-Out4 that forms a redistribution layer on top of the wafer and expands (fans out) the contacts beyond the dimensions of the chip, and Embedded Multi die Interconnect Bridge (EMIB)5 that uses a very small silicon die with multiple routing layers, that serves as an in-package interconnect. For electronic devices, thin and small semiconductor devices that are integrated at high density and can operate at high speed will continuously be required.