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CAD Tools and Design Kits
Published in John D. Cressler, Measurement and Modeling of Silicon Heterestructure Devices, 2018
Design projects are comprised of several phases, specification definition, design, and manufacture. The design phase spans the flow inputting information from the specification phase and outputting information to the manufacturing phase (Figure 8.1). To facilitate a design, computer-aided design (CAD) tools are integrated into the flow and customized to aid the designer. A process design kit (PDK) is a complete set of building blocks that are critical for any custom-integrated circuit design. The fundamental elements of a PDK consist of documentation, models for device and macros, schematic symbols, simulation support, physical design elements for device and routing options, technology files and physical verification rule decks for manufacturability and signal integrity. PDK development and support integrated into pure play foundry have proven an essential edge for foundries and customer-owned tooling (COT) vendors. A proven design methodology flow can take years to develop and is continuously improving to address the rapid transitions of technologies to tighter lithography and broader frequencies.
Model-Based Verification
Published in John D. Cressler, H. Alan Mantooth, Extreme Environment Electronics, 2017
The vertical axis represents complexity of the circuits comprising the ASIC. The horizontal axis represents the resources it takes to create them. The left branch of the V-diagram represents implementation tasks such as the creation of schematics, layout, and test benches. Note that the implementation begins with a specification or “Spec.” The bottom of the V-diagram is the process design kit (PDK), which is an electronic representation of a semiconductor process. The right side of the V-diagram represents verification tasks such as layout versus schematic (LVS) checking, running simulations that show interoperability of the ASIC circuits, and concludes with a release of the design to manufacturing, or “make.” The last step is made with trepidation as it commits the design to an unrecoverable tooling and manufacturing expense. Unfortunately, the economies of scale afforded to us by Moore’s law [2] work in reverse during new product development so it is much more important to have a functional first pass through the V-diagram on a 90 nm process than it is on a 0.35μm process. If the IC comes back from the foundry with problems, the V-diagram must be recycled and the verification branch must be improved to reproduce and fix the problem.
From Transistors to Circuits to Systems
Published in John D. Cressler, Silicon Earth, 2017
Here goes. Brace yourself for a deluge of jargon! Each company that serves as an IC “foundry” (maker of ICs for anybody with dollars to pay) provides the circuit designer (in this case, Peter) with what is known as a “Process Design Kit” (PDK). The PDK contains a ton of stuff: the “design rules” (how close lith pattern X can be to lith pattern ϒ) for each of the dozens of lith layers needed to build up the transistor and other circuit components (Rs, Ls, Cs, and interconnect wiring to tie them all together); “P-cells” (prototype designs of various components), complete with the “lay-out” of all the lith layer shapes arranged as needed (Figure 9.4 is a simple example); “compact models” (an electrical representation of the transistor(s) and other components to be used—e.g., how the I, V of the transistor depend on time) required to do complex “circuit simulations” (how does the circuit behave electrically as I alter this or that element of the schematic), various checking tools (e.g., DRC—Design Rule Checking, just what it says; LVS—Logical Verification System, which checks to make sure that what you think is connected, actually is) to make sure you did things according to the PDK’s many mandates, tons of documentation of how this particular IC technology is constructed and is supposed to behave, all sorts of reliability guidelines on what to do and not do if you want the fabricated objects to behave as advertised during the time it is in use in your system. On and on it goes. Whew! Each IC technology “platform” (just what it says) and each technology vendor (e.g., 32 nm CMOS technology from company X) has its own dedicated PDK. And each PDK runs (executes) under a massive software control package (remember those intelligent machines that coded the Matrix?!) using a collection of graphical user interfaces (GUI—pronounced ‘gooey’) and menus to make them friendlier to use.
From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology
Published in IETE Journal of Education, 2019
In view of the need of the academia to efficiently utilise SCL’s fabrication facility, this tutorial paper aims at providing all the requisite information and guidance that might be needed in this direction. The paper as such is written from the perspective of an Analog VLSI designer, mainly utilising CAD tools like Cadence Virtuoso, Cadence Spectre [9], and Mentor Graphics Calibre [10]. Nonetheless, the paper should be helpful for Digital designers as well. Various aspects right from transistor level design to tape-out in SCL’s 180 nm PDK (Process Design Kit) particularly issues like LVS (Layout Versus Schematic), PEX (Parasitic Extraction), post-layout simulation, I/O ring, fullchip DRC (Design Rule Checking), dummy metal fill, GDS file generation, etc. have been discussed. Such information is usually not available readily leading to substantial loss of time and effort on part of both the academic designer and the concerned liaison from SCL. The paper strives to bridge this information gap by building on the knowledge and experience gained during the course of chip design and submission to SCL while being supported by SCL engineers during the process.