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Thick-Film Materials
Published in Roydn D. Jones, Hybrid Circuit Design and Manufacture, 2020
Several low-permittivity, nonferroeleetric dielectric materials based on magnesium titanate, zinc titanate, titanium oxide, and calcium titanate are available. Dielectric constants are in the range 12 to 160, with temperature coefficients of ±200 ppm/°C. By varying the proportions of magnesium and/or zinc oxide to titanium oxide, compositions are possible having a NPO characteristic. [Negative positive zero (NPO) means that the temperature coefficient goes from a negative value to a positive value over the temperature range of interest.] High-K dielectrics are not as stable as low-K dielectrics. High-K dielectrics exhibit a slow reduction in capacitance with time. The change tends to be most rapid in the period immediately after firing, with relatively slow aging thereafter. The changes may be of the order of several percent. Low-K dielectrics are significantly more stable than higher-K types and should be used in cases where capacitance drift is a critical parameter.
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Published in Robert Doering, Yoshio Nishi, Handbook of Semiconductor Manufacturing Technology, 2017
For the lowest possible capacitance between metal lines, vacuum is the naturally best medium. However, vacuum cannot provide mechanical protection and support to the device interconnect metallization. SiO2 has been the primary material used for IMD electrical insulation in multi-level interconnects. The choice of SiO2 was based on its good dielectric and mechanical strength, as well as, the ease of processing. However, SiO2, with a dielectric constant ranging from 3.9 to 4.5 depending on formation methods, is not believed to be applicable in devices with geometries below about 0.18 μm because of its capacitance limitation. Various new materials—Si-based, C-based or a combination of both—have been mentioned as viable low k dielectrics of the future because of their dielectric constants from 3.7 to below 2.0 [60–64].
Bottom-Up Approaches for CMOS Scaling in the Nanoscale Era
Published in James E. Morris, Krzysztof Iniewski, Nanoelectronic Device Applications Handbook, 2017
Mrunal A. Khaderbad, V. Ramgopal Rao
Resistor–capacitor (RC) parasitics play a prominent role in overall chip performance in ultra-large scale integration (ULSI) technologies. That is why, in current technologies, copper metallization is used due to its lower resistivity (1.8 μΩ cm) as compared with traditional Al metallization (3.3 μΩ cm) [38,39]. In addition, the low-k dielectric between interconnects results in a significant reduction in RC delay, extending the performance enhancement curve for at least one technology generation [40]. Among various low-k materials, silsesquioxane (elementary unit (R–SiO3/2)n)-based dielectrics, with a k value less than that of SiO2’s relative permittivity, such as HSQ and methyl-silsesquioxane (CH3–SiO3/2 (MSQ)), have been widely explored [41,42]. Amorphous carbon and polymers have also been explored for BEOL purposes [43,44]. Lowering the k values in silica-based materials can be achieved by doping with fluorine or carbon or by introducing CH3 groups [45]. Also, BD is a low-k film from Applied Materials, consisting of PECVD organosilicate material with a changeable organic phase [46]. Though Cu/low-k technologies provide solutions to CMOS scaling, there are reliability issues such as copper diffusion through ILD, copper drift, poor adhesion, and thermal stability [47,48].
Effect of Young’s modulus on fracture characteristics of SiCO-SiCN multi-layer films by XFEM simulations of nano-indentation
Published in Mechanics of Advanced Materials and Structures, 2023
Jixi Deng, Xiuhuai Xie, Miao Zhang, Ningbo Liao
With increasing demands on very large scale integration (VLSI), interconnection delay becomes more critical due to its restriction on the speed of chip. In order to reduce the delay, advanced metal interconnection technologies combining low-k dielectric constant medium with metal are developed [1]. It requires the interconnection medium to have good mechanical strength and enough thermal stability [2]. Low-k thin film presents poor performance on mechanical properties, limiting its applications in below 90 nm structures [3]. The mechanical performance of low-k film is significantly influenced by interfacial failure, and leads to current leakage problems [4, 5]. Thus, designing low-k thin films system with excellent intermetallic dielectric properties and interfacial mechanical strength is important for the next generation of VLSI.
Correlation of Core Thickness and Core Doping with Gate & Spacer Dielectric in Rectangular Core Shell Double Gate Junctionless Transistor
Published in IETE Journal of Research, 2021
Vishal Narula, Amit Saini, Mohit Agarwal
According to the international roadmap of semiconductors (ITRS) the CMOS technologies demands for oxide thickness of 1 nm or less for better current drivability and effective control over the carriers [33]. The oxide thickness of 1 nm or less requires approximately two-three layers of SiO2 atoms. This can increase the direct tunneling of the carriers from the oxide and can lead to the increase in gate leakage current resulting into large power dissipation [34]. Therefore, key areas to improve the performance of the device is to replace the conventional dielectric SiO2 with high k gate dielectric which can reduce the gate tunneling current [22,35,36]. The high k dielectric results into fringing induced barrier lowering which deteriorates the performance of conventional MOSFET and FinFet [37,38], whereas an improvement in ON current is observed in tunnel FET [39]. However, device performance has been declined using high k spacers for TFET [39]. For double gate TFET a high-k dielectric and low-k spacer has improved the ON current compared to high-k spacer and high-k dielectric [40]. Thus, it is highly important to understand that impact of low-k and high-k gate dielectric combined with low-k and high-k spacer dielectric and vice versa are different for different architectures. In our previous study [28], gate/dielectric engineering has been studied for channel length 5 nm, however, the response of gate dielectric and spacer dielectric on the performance of RCS-DGJLT with varying core thickness and core doping is not yet explored in the literature best to our knowledge. The correlation between the parameters of the core and gate/spacer dielectric for magnificent performance of the device needs to be studied.
Performance enhancement of core-shell JLFET by gate/dielectric engineering
Published in International Journal of Electronics, 2020
Moreover, it is also observed that OFF current has shown a drastic improvement when HfO2 is taken as gate dielectric (HfO2 has higher dielectric constant than SiO2 and Si3N4) with aluminium as gate electrode (4.2 eV). This is because (1) HfO2 as dielectric provides a thicker physical gate dielectric layer keeping effective oxide thickness constant which leads to offer better gate control over the carriers and (2) larger work function difference between semiconductor and aluminium (4.2 eV) as gate electrode leads to volume depletion (Samia & Bouaza, 2013a). The extracted performance parameters are listed in Table 5. To figure out the importance of RCS based JLT architecture, it is observed from ref. (Samia & Bouaza, 2013b) that conventional MOS at gate length 13 nm using HfO2 as gate oxide exhibits ON/OFF ratio of ∼105 whereas, in our study using RCS architecture an ON/OFF current ratio of 107 is observed for gate length 5 nm using HfO2. It is also observed that DIBL attains lower value for HfO2 as high K dielectric as compare to low K dielectrics. This is probably because HfO2 offers better gate control on carriers and has capability to achieve volume depletion which avoids lowering of threshold voltage as compare to SiO2 and Si3N4. The poor value of DIBL is observed for low K dielectric materials due to lesser supervision over the carriers at zero gate voltage and therefore decreasing threshold voltage (Liu, Lu, & Guo, 2013). Clearly, better DIBL for lesser channel length is obtained by combining high K dielectric, aluminium as gate electrode along with core-shell architecture.