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A 3.3V GaAs Power MESFET for Digital/Analog Dual-mode Hand-held Phone
Published in Jong-Chun Woo, Yoon Soo Park, Compound Semiconductors 1995, 2020
Jong-Lam Lee, Sung-Jae Maeng, Haecheon Kim, Jae Kyoung Mun, Chang-Seok Lee, Jae Jin Lee, Kwang-Eui Pyun, Hyung-Moo Park
The optimum impedances for the output power and PAE of the first and second MESFETs were measured by the load/source-pull method using input and output tuners. Optimum impedance matching points for both source and load sides were searched by source pull and load pull methods, followed by power sweeping to measure the power performance of the device. Figure 6-(a) and -(b) displayed power and efficiency contours for the second FET using source pull and load pull measurements, respectively. The source pull measurement was done at a load impedance of Γ = 0.793 / -165.8o, which is marked as "Δ" in Fig. 6-(a). The source impedance for both maximum output power (mark of ■) and the maximum PAE (mark of ♦) coincide with each other, as shown in Fig. 6-(a). The load pull measurement was performed at a source impedance of Γ = 0.882 / -174.8O, which is marked as "Γ" in Fig. 6-(b). In the load pull measurement, we obtained a maximum PAE of 85.4% with an output power of 29.7 dBm at a load impedance point of Δ = 0.825 / -178.6O, marked as "◆". An maximum output power of 33.1 dBm with an PAE of 58% could be obtained a load impedance point of Γ = 0.773 / -159.3O.
Theory of High-Power Load-Pull Characterization for RF and Microwave Transistors
Published in Mike Golio, Commercial Wireless Circuits and Components Handbook, 2018
Load-pull as a design tool is based on measuring the performance of a transistor at various source and/or load impedances and fitting contours, in the gamma-domain, to the resultant data; measurements at various bias and frequency conditions may also be done. Several parameters can be superimposed over each other on a Smith chart and trade-offs in performance established. From this analysis, optimal source and load impedances are determined.
Wearable Communication and IOT Systems Basics
Published in Albert Sabban, Wearable Systems and Antennas Technologies for 5G, IOT and Medical Systems, 2020
Load pull: Load pull is the process of varying the impedance seen by the output of an active device to other than 50 Ω in order to measure performance parameters, in the simplest case, gain. In the case of a power device, a load pull power bench is used to evaluate large signal parameters such as compression characteristics, saturated power, efficiency and linearity as the output load is varied across the Smith chart.
A millimetre-wave GaAs monolithic multifunctional quadrupler chip with high harmonic rejection and high output power flatness
Published in International Journal of Electronics Letters, 2022
Ce-Tian Wang, Hai-Feng Wu, Wei Tong, Yu-Nan Hua, Yi-Jun Chen, Liu-Lin Hu, Ji-Ping Lv, Qian Lin
A1 labelled in Figure 1 is a fundamental linear driver amplifier working at 8–9 GHz, with a drain-biasing voltage of 4.7 V. The circuit schematic of A1 is shown in Figure 2. The input matching network is designed using C2, C3, T2, T3, R2 and C4, as Altaf et al. (2019). A standard CPW transistor device with sizes 2 × 75 μm has been used in this section. Based on the load-pull and source-pull simulation, the output and input matching circuits are designed targeting the optimal impedances to obtain the maximum gain and power. Considering the stability, the amplifier is biased using a current limiting resister R1 (as shown in Figure 1) to the gate. Meanwhile, decoupling capacitors C1 and C5 are optimised in drain-biasing circuit to enhance the low frequency stability. As a pre-driver amplifier, A1 provides an adequate input power for the quadrupler-stage, and this makes the quadrupler working at the optimal state to multiply the low frequency single with a low conversion loss.
A Holistic Experimental Static Bias Point Identification Method for Low Power Wireless RF Amplifier
Published in IETE Journal of Research, 2022
Saroj K. Patro, Rabindra K. Mishra, Ajit K. Panda
A 4 watt LDMOS RF power amplifier device [NXP, MW6S004NT1] Q1 is chosen whose operating frequency range is around 2 GHz [27]. An RF simulation tool [28] is used to simulate the circuit related performance parameters and their optimizations. Through the DC simulations, a quiescent drain current of 50 mA is obtained with a gate bias of 2.77 volts and drain bias of 28 volts. Load-pull and source-pull techniques are used to derive the optimum load and source impedances for delivering best combinations of peak power, linearity and power gain. The overall gain of the amplifier circuit is the combination of the gain contributions from the three factors, namely the intrinsic gain of the LDMOS device, gain or loss due to the input match, and gain or loss due to the output match and the same is governed by the unilateral transducer gain of a linear amplifier, which is often decided by the following equation, [29]: where S21, S11, S22 are the port parameters and GS and GL are the source and load reflection coefficients respectively. The above equations is valid for a simultaneously load and source conjugate matched scenario. Following this, the source side matching topology has been derived by using the circuit synthesis methods.