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Multicore Architectures and Their Applications in Image Processing
Published in Sanjay Saxena, Sudip Paul, High-Performance Medical Image Processing, 2022
T. Venkata Sridhar, G. Chenchu Krishnaiah
If the task is larger than the execution time will increase in single-core systems. Hence in the design of multicore processor architectures, the instruction-level parallelism (ILP) is inevitable that can handle multi-threads parallelly to speed the execution process and reduce the execution time compared with single CPU systems. ILP is a measure of how many independent instructions in a computer can execute parallelly. The classification of ILP-architecture is in three configurations [14]: Sequential-Architectures: In this architecture, parallelism is ambiguity as no clear information is there from the program regarding parallelism. Here superscalar-processors handle ILP.Dependent-Architectures: In this architecture, parallelism has no ambiguity as clear information is there from the program regarding parallelism. Here dataflow-processors handle ILP.Independent-Architectures: In this architecture, parallelism has no ambiguity as clear information is there from the program regarding parallelism and operations that are independent of each other. Here Very long instruction word (VILW)-processors handle ILP.
Towards Multicores: Technology and Software Complexity
Published in Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Design of Cost-Efficient Interconnect Processing Units, 2020
Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi
Furthermore, in recent years, Instruction Level Parallelism (ILP) has also been exploited for the simultaneous execution of several instructions, possibly out of order. However, ILP relies heavily on complex hardware structures to achieve more work per processor cycle, such as speculative branch prediction, multiple instruction issue, dynamic scheduling, non-blocking caches, and deep pipelines. Moreover, increasing the clock-rate, more and more instructions could be executed, but, in modern applications, locating instructions that can be executed in parallel, e.g. by a compiler, is a very hard task. In fact, all the intrinsic ILP is nearly fully utilized by today’s processors; therefore, there is no more possibility to increase performance as it has been achieved in the past.
Pipeline Architecture
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
Instruction–level parallelism (ILP) can be effectively realised by means of pipelining, superpipelining, and then more aggressively by the use of superscalar architecture employing more hardware resources within the processor. To further improve the throughput, designers have created even more complex mechanisms, such as the execution of some instructions in an order different from the way they occur in the instruction stream (out-of-order execution). All these architectures, however, extract ILP by means of a single stream of executing instructions, i.e. a single thread of execution. These processors are often found to have suffered from many different types of dependencies among machine instructions that often limit the amount of parallelism thus obtained. The dependences may be resource dependencies, control dependencies caused mostly by the presence of conditional branch instructions, or true data dependencies (RAW). Here, we are not considering WAR and WAW, because they can be efficiently handled using some form of register renaming.
Robust deadlock control in automated manufacturing systems with unreliable resources based on an algebraic way
Published in International Journal of Production Research, 2023
In this paper, our focus is to develop a robust control strategy for AMSs with multiple unreliable resources such that the continuous operations can be achieved even if some unreliable resources fail to work. During the evolution of the system net, the occurrence of deadlocks is related to the appearance of an unmarked siphon. Thus, we use a mathematical approach to detect an unmarked siphon at an illegal marking. A control specification is proposed to derive a control place with its related transitions such that the siphon cannot be emptied even if resource failures occur. Iteratively, a robust deadlock supervisor is finally synthesised to prevent deadlocks from appearing. Our method can apply to more general system nets in which each stage can acquire different type of resources. Through some examples, the results show that our method can derive a simpler supervisor in its structure and preserve more permissive markings. In our method, however, the considered AMSs only allow to acquire one unit of multiple types of resources at each processing stage. Future work will extend the proposed method to more complex system nets with multi-quantity and multi-type of resources. Furthermore, the achievement of our proposed method is based on an algebraic way. The complexity of ILP can affect the method's scalable application on real systems. We will continue to optimise the method to generalise its applications.
Double-Link Failure Protection Using a Single p-Cycle
Published in IETE Journal of Research, 2022
Pallavi Athe, Yatindra Nath Singh
The computational complexity of the ILP considerably depends on the number of variables and constraints; ILPs with many variables and constraints can be solved reasonably [34]. In this section, we compute the complexity of the SG method. The complexity of double-link protection methods [25], DB, IDB, and LPM methods complexity computation is provided in [28]. Let G(N, L) be a network graph with the N and L number of nodes and links, respectively. P represents the set of cycles for the network, and K is the working capacity on a link. Fill the text from your manuscript in different sections.
Exploration for Software Mitigation to Spectre Attacks of Poisoning Indirect Branches
Published in IETE Technical Review, 2018
Baozi Chen, Qingbo Wu, Yusong Tan, Liu Yang, Peng Zou
Exploiting ILP is one of the key goals in high performance processor design. Many techniques have been developed to maximize ILP. Branch prediction and speculative execution are two representative methods and have been adopted widely in modern superscalar processors.