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ZnO-Based LEDs
Published in Zhe Chuan Feng, Handbook of Solid-State Lighting and LEDs, 2017
Besides As-, P-, and Sb-doped p-type ZnO, N–In codoped p-type ZnO has also been used in ZnO nanowire (nanorod) array LEDs. Wu’s group [198] reported that ZnO homojunction LEDs based on ZnO nanowires were fabricated on Si (100) substrates. An N–In codoped p-type ZnO film grown by ultrasonic spray pyrolysis and an unintentionally doped n-type ZnO nanowire quasi-array grown by an easy low-temperature hydrothermal method were employed to form the homojunction diode. EL emissions of as-fabricated ZnO homojunction LEDs were observed under various forward biases. Typical EL spectra of the diodes showed evident UV peaks at 386 nm and broad greenish bands centered at ∼540 nm. It was concluded that the EL emission was contributed by the ZnO nanowires. The intensities of both UV and green emissions grew nearly linearly with the current.
AlGaN/GaN HEMT Modeling and Simulation
Published in D. Nirmal, J. Ajayan, Handbook for III-V High Electron Mobility Transistor Technologies, 2019
The semiconductor junctions are classified into two types: homojunction and heterojunction. When a semiconductor junction is formed of similar crystalline semiconductors having equal band gaps, it is called homojunction; whereas any junction that is formed of different band gaps semiconductors is called heterojunction. To form a heterojunction, the compound semiconductor material is preferred for its various advantages. In the compound semiconductor materials, band gap engineering is possible and suitable for high-frequency applications due to many compound semiconductors having larger carrier mobility. As shown in Table 10.3, the materials majorly have direct band gap semiconductors, therefore, it is also appropriate for optoelectronic devices fabrication.
Transistors: Lite!
Published in John D. Cressler, Silicon Earth, 2017
We’ll start with the simplest embodiment of a pn junction—the pn “homojunction.” Homojunction just means that within a single piece of semiconductor (e.g., silicon), we have a transition between p-type doping and n-type doping (e.g., p-Si/n-Si). The opposite would be a pn heterojunction, in which the p-type doping is in one type of semiconductor (e.g., p-GaAs), and the n-type doping is within another type of semiconductor (e.g., n-AlGaAs), to form a p-GaAs/n-AlGaAs heterojunction. More on heterojunctions later. As shown in Figure 8.6, there are several ways to build pn junctions. I might, for instance, ion implant and then diffuse n-type doping into a p-type wafer. The important thing is the resultant “doping profile” as you move through the junction [ND(x) – NA(x), which is just the net doping concentration]. At some point we have ND = NA, and thus a transition between net n-type and p-type doping. This point is called the “metallurgical junction” (x0 in the figure), and all of the action is centered here. To make the physics easier, two simplifications are in order: (1) Let’s assume a “step junction” approximation to the real pn junction doping profile; which is just what it says, an abrupt change (a step) in doping occurs at the metallurgical junction (Figure 8.6). (2) Let’s assume that all of the dopant impurities are ionized (one donor atom yields one electron, etc.). This is an excellent approximation for common dopants in silicon at 300 K.
Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic
Published in International Journal of Electronics, 2023
Lokesh Boggarapu, Sai Pavan Kumar K, Pown M, B Lakshmi
For delay calculations, delay is the time required for a signal to rise 10% to 50% of the supply. From the simulation window, the calculator is accessed and delay is chosen in which threshold values of 0.08 V and 0.4 V are given as 10% and 50% of supply voltage 0.8 V and the obtained expression from the delay functional panel is evaluated in the calculator (Cadence Tutorial2: Schematic Entry & Digital Simulation, 0000). For the design of TFET, it is assumed that (i) PTFET has the same drain characteristics and but only inverted and (ii) the capacitance values of drain and source of both PTFET and NTFET are the same and as small as 0.2 fF. This makes their intrinsic gate delays the same and makes both equally strong to produce the same rise and fall times to avoid sizing of transistors. The SS of the simulated device is found to be 34 mV/decade for homojunction TFET and 56 mV/decade for heterojunction TFET, which explains the ION/IOFF ratio from Table 2. Also, since the barrier width in the heterojunction is lower than that in homojunction TFET, ION and IOFF are high in heterojunction TFET, which explains the increase of SS from homojunction TFET to heterojunction TFET. However, the same devices when being used, heterojunction TFET gives better performance because of its double gate structure.
60 GHz Source for WLAN Applications Based on IEEE 802.11ad Protocol Standards
Published in IETE Journal of Education, 2019
Prajukta Mukherjee, Aritra Acharyya
Two important ratios (VD/VB) and (xA/W) have also been calculated. The above-mentioned DC parameters of HMDD, HTDD1 and HTDD2 diodes are given in Table 2. It is seen that the values of ξp at the metallurgical junction is slightly higher in heterojunction diodes than the homojunction diode. The value of VB in the heterojunction diodes are found to be significantly larger than the homojunction diode; however, the avalanche zone voltage drops in heterojunction diodes are found to be smaller due to the significantly narrow avalanche zone in those as compared to the homojunction diode. Larger (VD/VB)-ratio in heterojunction diodes indicate higher efficiency of HTDD1 and HTDD2 diodes than the HMDD diode [34]. Moreover, significantly smaller (xA/W)-ratio predicts the considerable amount of reduction in noise power (originates due to the random nature of the charge multiplication phenomena within the avalanche region) in the heterojunction DDRs as compared to their homojunction counterpart [26].
Metal halide perovskite: a game-changer for photovoltaics and solar devices via a tandem design
Published in Science and Technology of Advanced Materials, 2018
Heping Shen, The Duong, Yiliang Wu, Jun Peng, Daniel Jacobs, Nandi Wu, Klaus Weber, Tom White, Kylie Catchpole
The progress of 2-T perovskite/Si is also impressive, though the practical efficiency still lags that of the 4-T counterpart. This is understandable as the former structure strictly requires current matching and process compatibility between the two subcells. 2-T perovskite/Si tandem has been developed based on both crystalline Si homojunction and heterojunction solar cells. Notably, the former has dominated the PV industry with a global market share of approximately 93%, urging to integrate this commercially available product with high-efficiency perovskite solar cells and hence achieve low levelized electricity costs for the photovoltaic systems. In addition, the improved temperature tolerance of the c-Si bottom cell permits significantly increased flexibility in the design and fabrication of the perovskite cell. The first 2-T perovskite/Si tandem was published in early 2015 [71] with an efficiency of 13.7% based on an active area of 1 cm2, constituted by a Si homojunction solar cell as the bottom subcell, a heavily doped n-type Si thin film as the interconnection layer via tunnelling effect, and an n-i-p structure perovskite top subcell. The structure has an advantage of the tolerance for high-temperature treatment (over 400 degree). However, there has been no further publication on similar structure afterwards. One of the main reasons is due to the high recombination rates existing on the p++-Si surface, as it is difficult to introduce an effective passivation layer between p++-Si and n++-Si without deteriorating the charge transfer. Very recently, great progress has been achieved based on a high-temperature tolerant homojunction c-Si bottom subcell and a mesoscopic perovskite top subcell with a tandem efficiency of 22.5% (steady-state) and a Voc of 1.75 V on a 1 cm2 cell [72]. This is realized by a design of an array of metal contacts imbedded in the insulating Al2O3/SiNx passivation films on the front surface of c-Si solar cells, which enables efficient vertical charge transport for the bottom cells. This breakthrough indicates high possibility for commercialising efficient and inexpensive perovskite/c-Si tandem solar cells.