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Low-Power DSPs
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
On a traditional von Neumann architecture, 3N access cycles are needed to compute one output: for every tap one needs to fetch one instruction, read one coefficient, and read one data sample sequentially from the unified memory space. Already early on, DSP processors were differentiated from von Neumann architectures because they implemented a Harvard or modified-Harvard architecture [16,17]. The main characteristic is the use of two memory banks instead of one common memory space in the von Neumann architecture. The Harvard architecture has a separate data memory from program memory. This reduces the number of sequential access cycles from three to two because the instruction fetch from the program memory can be done in parallel with one of the data fetches. The modified Harvard architecture improves this even further. It is combined with a “repeat” instruction. In this case, one multiply–accumulate instruction is fetched from program memory and kept in the one instruction deep instruction cache. Then, the data access cycles are performed in parallel: the coefficient is fetched from the program memory in parallel with the data sample being fetched from data memory. This architecture is found in all early DSP processors and is the foundation for all following DSP architectures. It is an illustration of the “tuning” of the processor components to the application, in this case the memory architecture and the control logic.
Architecture and Instruction Set
Published in Julio Sanchez, Maria P. Canton, Embedded Systems Circuits and Programming, 2017
Julio Sanchez, Maria P. Canton
The PIC microcontrollers are not based on the von Neumann architecture that has been almost exclusively adopted in the computer world. The model of hardware design adopted for the PIC family is called the Harvard architecture. Harvard architecture refers to a computer design in which data and instruction used different signal paths and storage areas. Data and instructions are not located in the same memory area but in separate ones. One consequence of the traditional von Neumann architecture is that the processor can either read or write instructions or data but cannot do both at the same time, as both instructions and data use the same signal lines. In a machine based on the Harvard architecture, on the other hand, the processor can read and write instructions and data to and from memory at the same time. This results in a faster, albeit more complex machine. Figure 7-1 shows the program and data memory space in a mid-range PIC.
Digital Signal Processors
Published in Nihal Kularatna, Electronic Circuit Design, 2017
Harvard architecture refers to a memory structure in which the processor is connected to two independent memory banks via two independent sets of buses. In the original Harvard architecture, one memory bank holds program instructions and the other holds data. Commonly, this concept is extended slightly to allow one bank to hold program instructions and data while the other bank holds data only. This “modified” Harvard architecture is shown in Figure 7.10. The key advantage of the Harvard architecture is that two memory accesses can be made during any one instruction cycle. Thus, the four memory accesses required for the example FIR filter can be completed in two instruction cycles. This type of memory architecture is used in many DSP families, including Analog Devices ADSP-21xx.
Mixed Current Control Strategy for Bi-directional Boost Converter Fed BLDC Drive
Published in Electric Power Components and Systems, 2023
Chamarthi Sivarama Raju, Susovon Samanta
The microcontroller ATMEGA 2560 is cost effective and easy to use. The peripherals such as analog to digital converter (ADC), timers, UART (universal asynchronous receiver and transmitter), interrupt modules inside the microcontroller play a vital role. The microcontroller has the Harvard architecture, where separate memories for program and data are maintained. The resolution of the ADC is of 10 bits with a sampling rate of 1MSPS (million samples per second). The PWM generation for the control purposes achieved by using the timer modules. Since the clock frequency of the microcontroller is 16 MHz, smooth duty ratio control is possible for the present drive system. The controller code for the drive system is stored in the reprogrammable flash memory of the microcontroller.
50 years (and more) of German computer history
Published in International Journal of Parallel, Emergent and Distributed Systems, 2020
The programmes were often perpetuated in ROMs (nonvolatile read-only memories e.g. core rope memory or diode matrices7). This means that these computers contain separate programme and data memory (Harvard architecture). Only a few of these computers enjoyed the luxury of saving programmes variably in their central memory. The desktop form, well known from the past, was preserved as the main form of housing in a lot of cases.