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Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
Figure 14.126 illustrates gain compression characteristics of a typical microwave amplifier with a plot of output power as a function of input power. At low power levels, a single frequency signal is increased in power level by the small signal gain of the amplifier Pout =G*Pin . At lower power levels, this produces a linear Pout versus Pin plot with slope =1 when the powers are plotted in dB units as shown in Figure 126.14. At higher power levels, nonlinearities in the amplifier begin to generate some power in the harmonics of the single frequency input signal and to compress the output signal. The result is decreased gain at higher power levels. This reduction in gain is referred to as gain compression. Gain compression is often characterized in terms of the power level when the large signal gain is 1 dB less than the small signal gain. The power level when this occurs is termed the 1dB compression point and is also illustrated in Figure 126.14.
Linearization Techniques
Published in John D. Cressler, Circuits and Applications Using Silicon Heterostructure Devices, 2018
Leo C.N. de Vreede, Mark P. van der Heijden
Two other nonlinear phenomena that we can quantify using a single-tone excitation is the DC-shift due to self-biasing and gain compression or expansion. As we can see from (6.7), the self-biasing (12a2A2) is a second-order nonlinear effect and yields an increase in the DC-bias current. Gain compression or expansion can be explained by inspecting the fundamental amplitude in (6.7). We see that as the input signal amplitude A rises, the factor 34a3A3 (depending on the sign of the cubic term a3) may cause an increase or decrease of the fundamental signal (i.e. gain expansion or compression, respectively). For example, the cubic term of the CE configuration in (6.4) has the same sign as the linear term, leading to some gain expansion. On the other hand, the cubic term of the differential pair in (6.6) has an opposite sign with respect to the linear term, leading to gain compression at high drive levels. In fact, also the CE configuration will suffer from gain compression at some point. However, this will be due to other, strong nonlinear effects such as signal clipping to the supply voltage or saturation of the collector current (see “Hard Nonlinearities and Clipping” section), which are generally not described properly by a power series expansion. In general, gain compression is quantified by the 1 dB gain compression point (P1dB) and is defined as the input or output power level where the gain has dropped 1 dB with respect to the small-signal gain.
Board-Level Ku-Band Power Amplifier: Design and Challenges
Published in IETE Journal of Research, 2022
Hemant Kumar Singhal, Karun Rawat
A PA has been designed at 17 GHz frequency using a 6 W GaN pHEMT bare die device (CGHV1J006D) from Cree. The simulations are performed on Keysight’s Advanced Design System (ADS) software. The transistor is biased in class AB mode with a drain current of 90 mA and a drain voltage of 40 V. Usually a biasing circuit consists of DC feed network and by-pass capacitors, as shown in Figure 7. A T-section is designed for the DC feed network. From this figure, one may observe that for 17 GHz signal it behaves like an open circuit and for DC it behaves as a short circuit. C1 and C2 are the bypass capacitors used to protect the DC source from high-frequency components. In this design, a non-linear device model provided by Cree has been used for stability and harmonic simulations in Keysight’s ADS. The device is stabilized for the operating frequency range. The upper cut-off frequency of this device is 18 GHz, which is close to the circuit’s operating frequency. Therefore, the main challenge of this design is to achieve a reasonable bandwidth, power, and efficiency at the right extremum of the operating frequency of the device. The circuit is realized on Roger’s 3003 with dielectric constant 3 and thickness 5 mil. In order to determine the optimum load, which delivers the required power and efficiency, load-pull has been performed in simulation. One can see the profile of load-pull in Figure 8. Red-points in the figure show the optimum loads for maximum power delivered and black-points show the optimum load for maximum drain efficiency (DE). Blue points are selected as an optimum load for matching where power and efficiency both are optimized. Figure 9 shows the schematic of the matched PA. One can see from Figure 9 that the input matching network consists of transmission lines TL0 and TL1 and the output matching network is designed using TL4 and TL7. DC blocking capacitors are also a part of the matching network. Figure 10 shows the results obtained in simulation for the designed PA at 17 GHz with ±200 MHz band around it. Figure 10(a) shows the plot of simulated gain and DE versus input power at the center and corner frequencies of operation. Figure 10(b) shows the plot of simulated gain and DE over 400 MHz frequency band at saturation. One can observe from Figure 10(a) that at the center frequency, the gain is 6.71 dB at saturation. However, at lower corner frequency, the gain at saturation is 6.11 dB and at an upper corner frequency, the gain is 6.15 dB. These results are obtained at 2.5–3 dB gain compression. One can see from Figure 10(b) that the simulated DE varies between 27.2% and 32.2% over the frequency range from 16.8 GHz to 17.2 GHz at 30 dBm input power. Simulated gain varies between 6.11 to 6.71 dB over the frequency band of operation.