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Fabless Intelligent Manufacturing
Published in Chinmay K. Maiti, Fabless Semiconductor Manufacturing, 2023
A business that is a dedicated semiconductor fabrication facility does not design its own ICs. The term “fab” refers to anysemiconductor fabrication plant, whether run as part of an IDM (like Intel) or as a foundry (like TSMC). An application-specific IC refers to a chip that is custom-designed for a specific application, rather than for a general-purpose application. This type of company that developed in the 1980s performed the physical design and manufacturing of these application-specific ICs for other semiconductor or systems companies. An IC that integrates all components of a computer or other electronic system into a single chip is known as a system-on-chip (SOC). On a single substrate, it may contain digital, analog, mixed-signal, and sometimes radio-frequency functions. A company that designs its chip but outsources the manufacturing to a third party, either a foundry or an IDM is called the fabless company. This is the prevailing business model today. Electronic design automation (EDA) companies make the software that is used to design all modern semiconductor devices. The three dominant EDA companies today are Synopsys, Cadence Design Systems, and Mentor Graphics.
Electrode structures
Published in Michael Pycraft Hughes, Nanoelectromechanics in Engineering and Biology, 2018
The development of dielectrophoresis was, for the first few decades, dominated by the use of machined, three-dimensional shapes such as rods, pins, and planes to generate nonuniform electric field shapes. While these geometries were eminently suitable for dielectrophoresis of cell-sized particles, they did have disadvantages — principally that trapping particles on the nanoscale required high voltages to generate sufficient nonuniformities (with corresponding problems with fluid heating, as discussed in Chapter 3) and shapes on this scale did not facilitate the building of enclosed field minima for easy observation of negative dielectrophoresis. It was with the adoption of techniques originated in the electronics industry for the construction of semiconductor devices (silicon chips) that electrode construction was revolutionized. Since the end of the 1980s, almost all the electrode structures used for dielectrophoresis have been microfabricated. It is worth noting that the term fabricated is used almost exclusively to describe electrode construction, a term adopted from the microelectronics industry. It is occasionally abbreviated to fab, hence the description of semiconductor fabrication facilities as fab labs. A range of microfabrication techniques exists for the construction of electrode structures, but the principal method employed is that of photolithography. Other methods exist for particularly fine electrode structures, the principal method being direct-write methods outlined in Section 9.2.5.
Semiconductors in Mobile Telecommunications
Published in Saad Z. Asif, 5G Mobile Communications Concepts and Technologies, 2018
Historically, the semiconductor companies controlled the entire production process from design to manufacture. However, complexity, cost, and faster time to market trends have shifted the priorities and the chip companies are becoming leaner and more efficient. Thus, now we have IDMs (Integrated Device Manufacturers), fabless semiconductor firms, semiconductor foundries, and intellectual property core developers. A brief description of these follows: IDMs design, manufacture, package, and sell, that is, run the entire process on their own. Companies like IBM, Samsung, and a few others fall under this category.Second are fabless semiconductor firms that design and sell hardware semiconductor devices/chips, however, they outsource the fabrication to specialized manufacturers, that is, semiconductor foundries. Qualcomm, Broadcom, and so on are fabless companies.The semiconductor foundry (or simply fabs) are fabrication plants where ICs are manufactured; this is the third category. Fabs fabricate the designs of other companies, such as fabless semiconductor companies. Foundries are mainly found in China, France, Germany, Ireland, Japan, Malaysia, Singapore, Taiwan, and the U.S.The fourth category consists of semiconductor intellectual property core developers, designers, and licensors. An IP (intellectual property) core or IP block is a reusable unit of chip layout design that is the intellectual property of one party and can be licensed to another party. An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. ARM Holdings, PLC, and Cadence Design Systems are the key firms in this category [4,6].
Development of dynamic scheduling in semiconductor manufacturing using a Q-learning approach
Published in International Journal of Computer Integrated Manufacturing, 2022
Yeou-Ren Shiue, Ken-Chuan Lee, Chao-Ton Su
Semiconductor wafer fabrication (FAB) is a capital- and technology-intensive process characterized by high economic volatility and high risk. Therefore, reducing costs, improving quality, and improving delivery performance have become increasingly imperative. Moreover, FAB is a highly complex, expensive, and time-consuming process; it involves hundreds of machines that are located across dozens of different workstations. Wafer lots are passed between these stations and are subjected to hundreds of operations before process completion. FAB involves multiple types of products, re-entrant production processes, and diverse manufacturing features. This complexity poses a major challenge in terms of developing an effective dynamic scheduling mechanism in the extremely competitive environment of FAB (Sarin, Varadarajan, and Wang 2011; Li et al. 2013; Ma et al. 2017).
Efficient Fab facility layout with spine structure using genetic algorithm under various material-handling considerations
Published in International Journal of Production Research, 2022
As the demand for semiconductors continues to increase, semiconductor manufacturing facilities (Fabrication, Fab) are being built around the world and their number is expected to grow even more in the future. Such a semiconductor Fab facility would require more than several billion dollars of initial investment for the development of micro-fabrication processes. Therefore, determining the Fab layout effectively, operating Fab efficiently, and supplying cost-competitive products continuously have become the core capabilities of semiconductor manufacturing companies to recover the initial investment cost. In particular, it is known that the effective facility layout determination is a strategic decision affecting production efficiency, which can reduce 10–30% of the total operating cost (Singh and Sharma 2005). In general, this is called as the facility layout problem (hereafter referred to as FLP), meaning which process needs to be placed where and how the material flow system needs to be connected between processes.
Q(λ) learning-based dynamic route guidance algorithm for overhead hoist transport systems in semiconductor fabs
Published in International Journal of Production Research, 2020
Semiconductor wafer fabrication facilities, known as fabs, have highly complicated production systems (Kim, Yu, and Jang 2016). For instance, the wafer processing in a fab for an advanced DRAM chip requires more than 500 repetitive processing steps on hundreds of different processing machines called tools – that is, a single wafer visits the same tool several times. A modern large-scale fab processes 300 mm wafers. When wafers are transported between tools they are contained in a lot called a FOUP, which typically stores 25 wafers. The lots are transported by an overhead hoist transport (OHT) system, which consists of hundreds of vehicles and guided rails called tracks that are hung from a ceiling as shown in Figure 1. Hereafter, vehicle and OHT are used to refer to the vehicle unit in an OHT system, and these terms are used interchangeably.