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Diffusion
Published in Kumar Shubham, Ankaj Gupta, Integrated Circuit Fabrication, 2021
A diffusion furnace is a carefully designed apparatus proficient of upholding uniform temperature between 600–1200°C with a feedback controller. The diffusion tube made of high purity fused silica must be handled with great care, one tube and slice carrier being used for each type of dopant to prevent contamination. The length of the tubes varies from 10 cm – 150 cm or more for industrial furnaces. For large tubes the insertion of the carrier is done mechanically from one end, the other end being used for flow of gases and dopants. The temperature of the furnace is gradually ramped up from 600°C after insertion of the wafers with a programmed temperature controller ramping up the temperature at a linear rate of 3–10°C/min. This is to avoid thermal shock to the wafers as well as to the tube and components. In practice the diffusion tube is always kept above 600°C and never permissible to cool to room temperature to avoid devitrification. A gas source diffusion system is shown in figure 6.16(a).
Fundamentals of Microfabrication and MEMS Fabrication Technologies
Published in Sergey Edward Lyshevski, Nano- and Micro-Electromechanical Systems, 2018
Doping processes are used to selectively dope the substrate to produce either n- or p-type regions. These doped regions are used to fabricate passive and active circuitry components, form etch-stop layers (a very important feature in buck and surface micromachining), and produce conductive silicon-based micromechanical devices. Diffusion is achieved by placing wafers in a high-temperature furnace and passing a carrier gas that contains the desired dopant. For silicon, boron is the most common p-type dopant (acceptors), and arsenic and phosphorous are n-type dopants (donors). The dopant sources may be solid, liquid, or gaseous. Nitrogen is usually used as the carrier gas. Two major steps in diffusion are predeposition (impurity atoms are transported from the source to the wafer surface and diffused into the wafer; the number of atoms that enter the wafer surface is limited by the solid solubility of the dopant in the wafer) and drive-in (deposited wafer is heated in a diffusion furnace with an oxidizing or inert gas to redistribute the dopant in the wafer to reach a desired doping depth and uniformity). After deposition, the wafer has a thin, highly doped oxide layer on the silicon, and this oxide layer is removed by hydrofluoric acid.
Fundamentals of MEMS Fabrication
Published in Sergey Edward Lyshevski, Mems and Nems, 2018
Doping processes are used to selectively dope the substrate to produce either n- or p-type regions. These doped regions are used to fabricate passive and active circuitry components, form etch-stop-layers (very important feature in buck and surface micromachining), as well as produce conductive silicon-based micromechanical devices. Diffusion is achieved by placing wafers in a high-temperature furnace and passing a carrier gas that contains the desired dopant. For silicon, boron is the most common p-type dopant (acceptors), and arsenic and phosphorous are n-type dopants (donors). The dopant sources may be solid, liquid, and gaseous. Nitrogen is usually used as the carrier gas. Two major steps in diffusion are predeposition (impurity atoms are transported from the source to the wafer surface and diffused into the wafer, the number of atoms that enter the wafer surface is limited by the solid solubility of the dopant in the wafer), and drive-in (deposited wafer is heated in a diffusion furnace with an oxidizing or inert gas to redistribute the dopant in the wafer to reach a desired doping depth and uniformity). After deposition the wafer has a thin highly-doped oxide layer on the silicon, and this oxide layer is removed by a hydrofluoric acid.
A state-of-art review and a simple meta-analysis on deterministic scheduling of diffusion furnaces in semiconductor manufacturing
Published in International Journal of Production Research, 2023
M. Vimala Rani, Muthu Mathirajan
Though there are many BPMs in wafer fabrication, this study focuses only on the diffusion furnace because around 30% of the total WIP (work-in-process) in a wafer fabrication is staying in the diffusion area due to its lengthiest processing time among all the operations in the wafer fabrication (Jung et al. (2014)). There are many published research articles on the scheduling of diffusion furnaces (SDF). In that, most of the research studies assumed the deterministic situation, and few studies considered the stochastic situation. The assumption on the deterministic situation in SDF is being justified by the researchers mainly due to (a) the longest processing time requirement of diffusion operation and (b) the computerised shop floor environment of wafer fabrication. Due to that, any occurrences of stochastic/uncertain event(s) can be taken care of by updating the required input, particularly those that are getting affected by the stochastic/uncertain event(s), for SDF. Hence, in this study, we present a state-of-art review of all existing literature and various simple meta-analyses on the deterministic scheduling of diffusion furnaces (D-SDF) only.
In-profile monitoring for cluster-correlated data in advanced manufacturing system
Published in Journal of Quality Technology, 2023
Peiyao Liu, Juan Du, Yangyang Zang, Chen Zhang, Kaibo Wang
In this diffusion process of semiconductor manufacturing, in-situ sensors located around a diffusion furnace are used for real-time data collection of each wafer (Zhang, Zhang, and Chen 2017). We analyze nine representative sensors and denote them as S1-S9, with S1-S6 shown in Figure 1(a). The time lengths of different samples vary from 190 to 240. Clearly, there exists clustered BPC structure in this case. For example, voltage sensors (S1 and S2) are jointly influenced by circuit power and local load; temperature sensors (S3, S4, S7-S9) are all depended on thermal energy; while pressure sensors (S5 and S6) are both affected by gas flow rate. Consequently, these sensors can be divided into three groups, and the four identified latent states can be regarded as circuit power, load, thermal energy, and gas flow rate. We have 28 IC samples in total. Since the real OC data are confidential, we generate OC signals to mimic the real OC situation as Figure 1(a) shows. These OC patterns are designed by engineers based on the true anomaly patterns in the manufacturing process. In particular, a slope shift occurs in early sensing points of S1 and S2. Also, both S5 and S6 have an earlier drop since time point
Multivariate bounded process adjustment schemes
Published in Quality Technology & Quantitative Management, 2018
Nirmal Govind, Enrique del Castillo, George Runger, Mani Janakiram
In this section, we demonstrate the approach that we have outlined in the previous sections using a simulated multivariate model based on a Vertical Diffusion Furnace process in the semiconductor manufacturing industry. In this process, the material is deposited on a batch of silicon wafers (usually around 125–150 wafers) and the objective is to maintain a uniform thickness of the deposited material on wafers in each of the zones of the furnace. This is done by controlling the temperature and deposition time. The fixed cost of adjustment in such a process is usually the impact on throughput time of making an adjustment. For example, if a certain amount of time is needed to reach the set temperature, this has a direct impact on the throughput of the tool. The process therefore has three responses and two inputs. The objective is to control the process and bring the responses to desired target values by adjusting these two inputs. Note that the parameters chosen below for the simulation case study do not reflect the actual parameters of the modelled process.