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Delta-Sigma Modulation of Three-Phase Matrix Converters
Published in Narayanaswamy P. R. Iyer, AC to AC Converters, 2019
This is a recently proposed technique for three-phase MCs [13–15]. In delta-sigma modulation, high-frequency noise peaks in the output voltages due to switching operation do not occur and this becomes an advantage for clearing noise regulations [13–15]. Figure 7.1a,b shows the first-order delta-sigma modulator [17]. Analysis of Figure 7.1a gives the following: X(z)−z−1*Y(z)+z−1*E(z)=E(z)
Low-Power Analog-to-Digital Converters (ADCs) for Mobile Broadcasting Applications
Published in Borko Furht, Syed Ahson, Handbook of Mobile Broadcasting, 2008
It was shown in (9.6) that oversampling can improve the SNR of an ADC despite circuit implementation. Thus, oversampling ADCs are more suitable for high-resolution (18 bits and more) implementations. Among all oversampling ADCs, the delta-sigma ADC is the most widely used. This is because it is the most robust ADC against circuit imperfections. Delta-sigma ADC employs the oversampling technique and the noise-shaping technique, which will be described as follows. A delta-sigma ADC consists of an analog delta-sigma modulator and the digital and decimation filter. A first-order delta-sigma modulator is shown in figure 9.12. It contains an integrator, a 1-bit ADC, a 1-bit DAC, and a subtractor. The name first-order stems from the fact that there is only one integrator in the circuit.
Power and Signal Integrity Challenges in 3D Systems-on-Chip
Published in Aida Todri-Sanial, Chuan Seng Tan, Krzysztof Iniewski, Physical Design for 3D Integrated Circuits, 2017
To manage computational complexity, the proposed signal integrity analysis focuses on a single channel that consists of a first-order delta-sigma modulator, counter for decimation, and shift register, as depicted in Figure 6.16 [86,87]. Delta-sigma modulator consists of a current integrator, comparator, and switched-current 1-bit D/A converter in the feedback loop. The counter is the primary aggressor, whereas the sense amplifier within the current integrator is identified as one of the primary victim blocks. The switching noise that couples from the counter to the sense amplifier is analyzed for different scenarios, as described in the following sections.
A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator
Published in International Journal of Electronics, 2020
Jaeseong Lee, Seokjae Song, Jeongjin Roh
With their advanced system requirements, analogue and digital circuits require ever-increasing data processing capabilities. Considering this, analogue-to-digital converters (ADCs) are one of the most important building blocks in communication systems. Among the various types of ADCs, delta–sigma modulator (DSM) can be used to achieve high resolutions (Matthew & Hua, 2009; Roh, Byun, Choi, & Roh, 2010) due to its noise-shaping property, and thus it is a frequently used architecture in communication systems (Mitteregger et al., 2006; Vleugels, Rabii, & Wooley, 2001) Recently, DSM has been widely used in wireless communication devices such as Bluetooth, 3GPP, or WIFI (Liang, Sai, Seng, Franco, & Rui, 2017; Ritter, Kauffman, Becker, & Ortmanns, 2015).