Explore chapters and articles related to this topic
Clock signal and its attribute for agriculture
Published in Govind Singh Patel, Amrita Rai, Nripendra Narayan Das, R. P. Singh, Smart Agriculture, 2021
DLL is the digital format of PLL, used to insert a delay in the clock signal to the desired value in accordance with the circuit it is included in the design. In usual emphasis, the clock timing properties are delayed, thereby increasing the output produced to an expected level and thus controlled. DLLs are also utilized for clock and data recovery (CDR) systems. To elaborate the functioning of a DLL utilized as a functional block, a negative delay gate is used with the clock reference input signal. It is a kind of PLL circuit only with the difference of the usage of a delay element in place of an oscillator circuit. The internal component of the DLL circuit contains a phase locator (PD) which compares the phase of the reference clock and feedback clock phase. Depending on the UP or DOWN signal of the reference clock, signal charge pump either charges upward or downward. They are shown in Figure 14.3. The charge pump output is filtered out through a low pass filter finally at the far end received by the delay line. Hence, with the phase locator circuitry input, the delay line gets delays in the output clock frequency to the phase locator. The delay line comprises cascaded connections of specific delay gates or combinational elements. The delay gates are in the form gates like inverters, NAND gate or the XOR gate.
A wide-tuning frequency range DLL-based clock generator
Published in Artde D.K.T. Lam, Stephen D. Prior, Siu-Tsen Shen, Sheng-Joue Young, Liang-Wen Ji, Smart Science, Design & Technology, 2019
Almost all electronic systems have a clock generator [1], and the clock generator determines the speed of the whole system, a good clock generator can greatly improve the performance and adaptability of the system. There are two ways to implement the general clock generator. One is to use the crystal oscillator. The other is to use the circuit technique and the crystal oscillator to realize the high speed and wide-tuning range of the clock generator. The crystal oscillator only generates a single frequency, which is only suitable for low-speed and simple systems. Generally, circuit techniques are used to improve output frequency of the crystal oscillator in order to make the system more high-speed and flexible. The circuit implementations are mostly divided into two methods .One is Phase Locked Loop (PLL)[2-3] the other is realized by using Delay-Locked Loop (DLL)[4-6] .The implementation of PLL has the advantages of high speed, easy to change the output frequency, and has many applications. Compared with the PLL-based clock generator, the DLL has many advantages, such as smaller area, faster locking time, unconditional loop stability and better performance of clock jitter. Therefore, in recent years, DLL is often used to replace PLL.
PLL Circuits
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Muh-Tian Shiue, Chomg-Kuang Wang
A typical application of DLL is to synchronize the clock edges of subsystems within a digital system to access the bus between subsystems. Figure 5.35 shows modern digital systems that use synchronous communication to achieve high-speed signaling to and from the bus between the subsystems. Subsystems that communicate synchronously use a clock signal as a timing reference so that data can be transmitted and received with a known relationship to this reference. A difficulty in maintaining this relationship is that process, voltage, and temperature variations can alter the timing relationship between the clock and data signals of subsystems, resulting in reduced timing margins. Figure 5.36 shows that on the left side the data valid window (the time over which data can be sampled reliably by the receiver) can be large at low signaling speeds [38]. Even in the presence of a substantial shift in the data valid window across operational extremes, the resulting data valid window can still be large enough to transmit and receive the data reliably. Unfortunately, the variations in process, voltage, and temperature can result in the loss of the data valid window when the signal speed is increased as also shown on the right-hand side of Figure 5.36. This problem gets worse as signaling speeds increase, limiting the ability of subsystems to communicate data at higher speeds.
Multi-phases all-digital DLL with multi-input and wide-range delay line
Published in International Journal of Electronics, 2021
Current computer and communications systems are required to process vast amounts of data, emphasising the importance of I/O interface transmission technologies. I/O interface transmission systems use delay-locked loop (DLL) architecture to produce synchronous clock signals. This type of I/O interface architecture is widely used in applications including SerDes used in computer chips and chip transmission where transmission speeds can exceed 1 GHz, or in the OpenLDI consumer LED television video interface specification (National Semiconductor, 1999) where transmission speeds are below 200 MHz. Because of the difference between computer and home appliance frequencies, DLL designs can be used in different systems requiring multi-phase and large-scale operation frequency range.
Implementation and Analysis of Grid-Based Ionospheric Correction Technique and Positioning Errors of NavIC + GPS ARAMIS SDR Receiver
Published in IETE Technical Review, 2022
Mehul V. Desai, Darshna Jagiwala, Shweta N. Shah
Doppler frequency and code phase estimates are generated by the correlation between the in-phase (I) and quadrature (Q) components of the input signal in the acquisition block and the local replica of the GNSS code. Here signal tracking follows signal acquisition, and on each receiver channel, a Delay-Locked Loop (DLL) is used to synchronize the received spreading code with the local replica, while a Phase-Locked Loop (PLL) is typically used to track the phase input carrier. Signal tracking is the basis for demodulating navigation messages, it relies on signal correlation and estimates distances between users and satellites.