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Digital Circuits
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
John P. Uyemura, Robert C. Chang, Bing J. Sheu
Now suppose that the inputs are switched to (A, B, C) = (1, 1, 0) during the evaluation phase. MOSFETs MA and MB are ON, but MC is OFF, blocking the discharge path. Charge sharing occurs because the charge originally stored on Cout is now shared with C1 and C2. After the transients have decayed, the three capacitors are in parallel, Ignoring any threshold drop, they will share the same final voltage Vf such that () QT=(Cout+C1+C2)Vf
Semiconductor Sensors for Direct X-Ray Conversion
Published in Yallup Kevin, Basiricò Laura, Iniewski Kris, Sensors for Diagnostics and Monitoring, 2018
The main signal degradation mechanisms are comparable to indirect-conversion scintillator detectors: First, fluorescence scattering takes place. Due to the lower K-edge energy, the mean free path lengths of fluorescence quanta in CZT are about 100 μm. The smaller the pixel size, the more fluorescent cross-talk will affect the behavior of the detector. Secondly, the charge signal transport is affected by charge sharing. The moving charge cloud also induces electrical pulses in neighboring pixels—again, mostly at the bottom part of the pixel field configuration.
Spatial and Spectral Resolution of Semiconductor Detectors in Medical Imaging
Published in Krzysztof Iniewski, Biological and Medical Sensor Technologies, 2017
The main signal degradation mechanisms are comparable with indirect conversion scintillator detectors: first, fluorescence scattering takes place. Due to the lower K-edge energy, the mean free path lengths of fluorescence quanta in CZT are about 100 μm. The smaller the pixel size, the more fluorescence cross talk will affect the behavior of the detector. Second, the charge signal transport is affected by charge sharing. The moving charge cloud also induces electrical pulses on neighboring pixels [14], again mostly at the bottom part of the pixel field configuration.
Design of energy efficient domino logic circuit using lector technique
Published in International Journal of Electronics, 2022
Km Anjali Verma, Manish Kumar, Saurabh Kumar, R. K. Chauhan
Domino logic gates are widely used in modern digital VLSI circuits because of the high-speed processor and lower transistor count (Shah et al., 2016). Domino logic offers less noise margin due to charge-sharing at internal nodes and leakage current. When compared to a static CMOS logic gate, it requires less area (Peiravi & Asyaei, 2012). Domino logic circuit attains high speed and is highly sensitive to noise due to low noise margin. The speed of the domino increases when there is a reduction in threshold voltage. In domino logic gates, evaluation is performed by only the NMOS transistor, which makes it a preferable circuit design.