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Performance analysis and comparison of 4-bit adder architectures
Published in Rajesh Singh, Anita Gehlot, Intelligent Circuits and Systems, 2021
Aishani Misra, Shilpi Birla, Neha Singh
There are several reports of work that has been done on adders. A comparison of 100-bit RCA and a CSA has been done by [1]. By using a poly biasing technique the PMOS/NMOS strength ratio was balanced [2] and was compared by 32-bit and 16-bit adders respectively, thus showing their proposal was more energy efficient. Speed and power efficient 4-bit CLA has been designed by [3] using pass transistor logic (PTL), on 180nm CMOS technology, because of which power consumption, delay and energy have been reduced. Various 32-bit carry-skip-adders were designed and compared [4] on 45nm CMOS technology and as per results concatenation and incrementation carry-skip adder has 51% improvement in the critical path delay and energy, compared with that of conventional carry-skip adder. Ultra-low power and low voltage adders were designed and analysed [5] with an extended body bias voltage to improve the functional yield and balance the pull-up and pull-down networks on 22nm FDSOI technology. Harikrishnan and Sethi [6] optimally designed Manchester carry chain adder and reduced the delay by 19% using linear and El-more delay model. Numerous studies [7,8] have looked at various adders namely parallel prefix adders (PPA), MCC etc.
A distinct carry celect adder design approach for area and delay reduction using modified full adder
Published in Arun Kumar Sinha, John Pradeep Darsy, Computer-Aided Developments: Electronics and Communication, 2019
K. Bala Sindhuri, G. S. Chandra Teja, K. Madhusudhan, N. Udaya Kumar
The carry skip adder (also called as carry bypass adder) skips the carry at appropriate positions to boost the operation speed and the time required for this operation varies with respect to the data. The carry look ahead adder reduces the delay due to the propagation of the carry by looking at the lower adder bits of data and carry from the higher orders. The CLA design is more complex and it consumes more area when designed for more than 4-bits. In CIA, it is designed with RCA and an additional circuit that generates increment. Finally, in CSA the design has reduced delay by storing the carry generated in the present stage and by updating it on the next stage.
C
Published in Phillip A. Laplante, Dictionary of Computer Science, Engineering, and Technology, 2017
carry-skip adder an adder in which the bit-stages are grouped into blocks, and carries are propagated between blocks, in such a way that carries may skip blocks (that would produce a carry) instead of rippling through. The skipping is faster than the rippling and so speeds up the adder.
Design of FIR Filter Using Low-Power and High-Speed Carry Select Adder for Low-Power DSP Applications
Published in IETE Journal of Research, 2023
Siliveri Swetha, N. Siva Sankara Reddy
Ripple Carry Adder (RCA) is the most common type of adders, but its main disadvantage is longer carry propagation delay. To overcome that many fast adders have come into existence like Carry Look-ahead Adder (CLA), CSLA, and Carry Skip Adder. Among these fast adders, CSLA is the fastest adder but large chip area and consumes more power as two blocks of RCA is used for Cin = 0 and Cin = 1 [3,4]. Since CSLA is a high-speed, low-power, and area-efficient adder, the suggested adder is better suited for FIR filters of high quality. When designing the FIR filter using an approximative adder/multiplier, the filter’s quality should be evaluated.