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Future of Asynchronous Logic
Published in Tomasz Wojcicki, Krzysztof Iniewski, VLSI: Circuits for Emerging Applications, 2017
Using dual-rail logic, timing is no longer needed to determine computation completion. Starting with the system in an all NULL state, DATA is input to the system, which flows through the combinational logic, eventually transitioning all of the outputs to DATA, which depicts that the computation has finished. The system must then transition back into the all NULL state before the next DATA wave front is input to the system. NORing the two rails of a dual-rail signal generates a Logic 0 when DATA and a Logic 1 when NULL, which can be used as an acknowledge signal. To signal when all outputs are DATA or NULL, to determine when the computation or return to NULL has finished, respectively, the acknowledge signals must all be combined together using what is referred to as a C-element [7]. A C-element only changes state when all inputs are the same; when all inputs are asserted, the output is asserted, which then remains asserted until all inputs are deasserted, which requires internal feedback within the C-element gate. The C-element output can then be used to request the next DATA wave front input when asserted, and the return to NULL when deasserted.
Signal Integrity and Reliability of Network-on-Chip
Published in Santanu Kundu, Santanu Chattopadhyay, Network-on-Chip, 2018
Santanu Kundu, Santanu Chattopadhyay
This section focuses on logic soft error protection—soft errors in latches, flip-flops, and combinational logic. Soft errors in SRAMs are protected using parity or error-correcting codes with interleaving. For a latch, as discussed in Section 7.2.3.2, the Q output is strongly driven by the D input during the active cycle of the clock and the latch is not susceptible to soft errors. In the inactive cycle when the output is latched to its previous state, soft error can cause a SEU. Mitra et al. (2006a) proposed a built-in soft error resilience (BISER) technique to protect the latches in the design using C-element. C-element is a special type of hardware where two PMOS and two NMOS transistors are connected in series. A two-input C-element and its truth table are shown in Figure 7.9. From the truth table, it is clear that if both the inputs of C-element are same, the output (C-OUT) will follow the inputs; otherwise, the output will latch at its previous value. Mitra et al. (2006a) presented the soft error correction in latches using C-element and a redundant latch as shown in Figure 7.10. If soft error affects any of the latches at a time, the output of the latches will differ and the C-OUT will retain to its previous value, and hence error will not propagate to the next stage. The correct logic value will be held at C-OUT by the keeper. Soft error in the keeper does not have a major effect because the C-element output will be strongly driven by the latch contents. The cost associated with the redundant latch is minimized by reusing on-chip resources such as scan for multiple functions at various stages of manufacturing and field use (Mitra et al. 2005).
Fault-Tolerant Asynchronous Circuits
Published in Wei Song, Guangda Zhang, Asynchronous On-Chip Networks and Fault-Tolerant Techniques, 2022
Logical masking plays an important role in asynchronous circuits. The use of C-elements, which are the most fundamental and important cells in asynchronous circuits, actually enriches the concept of logical masking. A C-element outputs 1 or 0 if both of its inputs are 1s or 0s; otherwise, it keeps its previous output. As shown in Figure 5.6, when iack is 0, a positive glitch at the other input of the 2-input C-element is masked. Similarly, when iack is 1, a negative glitch at the other input is masked. Only when a glitch at the input in flips to the same level with iack, the fault would be latched. However, such a fault might still be tolerated depending on the correct input and the timing of the circuit: Premature firing: As shown in Figure 5.7a, if the flipped output of the affected C-element is not quick enough to withdraw iack as the correct input signal arrives soon after the glitch, this fault actually produces a premature firing of the output. Instead of causing an error in the QDI circuit, this type of fault masking actually reduces the latency of this particular event.Prolonged firing: Similarly, a fault can prolong a firing if it happens soon after the correct input and with the same level, as shown in Figure 5.7b shows. Since iack does not rise before the fault caused glitch, the fault has no impact on the function but prolongs the timing.
An Innovative VCN Coating for High-Temperature Tribological Applications via Orthogonal Research
Published in Tribology Transactions, 2020
The surface and cross-sectional morphologies of the as-deposited VN and VCN coatings are shown in Fig. 3. As can be seen from Fig. 3a, the VN coating presents a rough surface with many conical, spherical, and ellipsoidal asperities and microcavities, which do not improve the roughness. These characteristics generated in the deposition process can have a detrimental effect on the mechanical and tribological properties of VN coating but are impossible to avoid in vacuum arc deposition. When C element is doped into the VN lattice to form the VCN coating, the number of microasperities and microcavities is decreased obviously, but the specimen surface shows a pronounced roughness, as shown in Fig. 3b. The average roughness of VCN coating is about 121 nm, and the value of VN coating is about 105 nm, a decrease of 13% without C-dopant. This result is consistent with the conclusions of Warcholinski et al. (56); that is, carbon doping of a nitride coating can increase the roughness of the sample surface. Figures 3c and 3d show that the specimen thicknesses of VN and VCN coatings are about 2.58 and 2.41 μm, respectively, which indicates that carbon doping of the VN coating results in a slight decrease in coating thickness. Figure 4 shows the EDS results of point 1 and point 2 on the VN and VCN surfaces, respectively. As can be seen, the C, N, and V elements are detected at energy levels of 0.26, 0.38, and 4.96 keV, respectively. In addition, from Table 2, the atomic percentage of C, N, and V elements is about 2.74, 19.92, and 77.34 at%, respectively, in the full scale of the VN spectrum, and the values of VCN coating are about 14.83, 11.03, and 74.14 at%, respectively. Apparently, the atomic percentage of C element greatly increases, and those of N and V elements show an obvious decrease after C element is doped into the VN lattice.