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Introduction to Compact Models
Published in Samar K. Saha, Compact Models for Integrated Circuit Design, 2018
In the meanwhile, BSIM has been continuously updated and extended to accurately model the physical effects observed in sub-100 nm regime. In 2000, BSIM4, version BSIM4.1.0, was released [55]. BSIM4 offers several improvements over BSIM3, including the traditional I–V modeling of intrinsic transistor, the transistor’s noise modeling, and the incorporation of extrinsic parasitics. Some of the salient features of BSIM4 are an accurate model of the intrinsic input resistance for RF, high-frequency analog and high-speed digital applications, flexible substrate resistance network for RF modeling, an accurate channel thermal noise model along with a noise partition model for the induced gate noise, an NQS model consistent with the gate resistance-based RF model, an accurate gate direct tunneling model, a geometry-dependent parasitics model for various source-drain connections and multifinger devices, improved model for steep vertical retrograde doping profiles, better model for halo-implanted devices in Vth, bulk charge effect model, and output resistance, asymmetrical and bias-dependent source-drain resistance, QM charge-layer model for both I–V and C–V, gate-induced drain/source leakage (GIDL/GISL) current model, and improved unified 1/f noise model [55–57].
Performance and Feasibility Model Generation Using Learning-Based Approach
Published in Soumya Pandit, Chittaranjan Mandal, Amit Patra, Nano-Scale CMOS Analog Circuits, 2018
Soumya Pandit, Chittaranjan Mandal, Amit Patra
For each input sample (transistor sizes) extracted through sampling strategy, the chosen circuit topology of a component block is simulated using SPICE. Appropriate BSIM model is to be used for simulation. For nano-scale technology, BSIM4 is to be used. This ensures that all important deep sub-micron effects of MOS transistors are considered while generating the dataset. Depending upon the selected input-output parameters of the NN model, it is necessary to construct a set of test benches that would provide sufficient data to facilitate automatic extraction of these parameters via postprocessing of SPICE simulation output files. The commonly used SPICE simulations are ac analysis, transient analysis, dc sweep etc. The voltages and currents at the various nodes of the circuit are also measured. In many cases, constraints are imposed upon the SPICE results to ensure that only feasible data are considered for model construction.
Compact Modeling of CMOS Devices
Published in John D. Cressler, H. Alan Mantooth, Extreme Environment Electronics, 2017
The Berkeley Short Channel IGFET Models (BSIM) remain the most widely used MOSFET models today. BSIM3 has remained relevant in bulk technologies at geometries above 100 nm since its introduction nearly 20 years ago [10], and is still widely used in many mixed-signal processes including 130 nm bulk silicon and 0.5 μm SiGe [11,12]. In bulk technologies below 100 nm, the MOSFET model of choice has been the fourth-generation Berkeley model, BSIM4 [13]. Introduced in 2000, it has served the IC industry well and is the dominant model at the popular 90 nm digital node. BSIM4 introduced many novel and now seen as essential effects for deep-submicron design, including a high-fidelity gate current model, impact ionization effects, draininduced barrier lowering, a single equation drain current model, and RF support through a detailed substrate model. For the future, surface potential MOSFET models, such as PSP [14], HiSIM [15], and BSIM5 [16], are seen as providing the best approximations of device behavior at ever smaller geometries [17]. PSP in particular has been chosen by the CMC as the successor to BSIM4 and is currently growing in popularity across a wide spectrum of processes. Another bulk MOSFET model of interest is EKV, which is popular in ultralow threshold circuit design and analog designs using the inversion coefficient technique [18].
Ultra-fast SRAM using spatial wave-function switched FET (SWSFET)
Published in International Journal of Electronics Letters, 2019
SRAM bandwidth is more than Dynamic RAM (DRAM) bandwidth because of opposite states in two bit lines at the time of read operation. A small voltage swing can be detected easily with SRAM because of its symmetric structure. SRAM is faster. The noise margin in a SRAM cell is improved because of the presence of two bit lines for signal and its inverse. The circuit model of SWSFET based on Berkley Short Channel IGFET Model (BSIM) 3.2.0 is discussed elsewhere (Karmakar & Jain, 2016; Karmakar, 2013c; Karmakar et al., 2012). The SRAM cell proposed in this paper is based on two unipolar inverter based on SWSFET where the architecture is different than previous published work (Gogna et al., 2012). In this proposed architecture, the architecture is similar to standard CMOS SRAM cell where PMOS is replaced by SWSFET. This structure output is more stable and they are fast because electron is only the charge carriers and SWSFET is designed in InGaAs material system where electron mobility is more than that of silicon.
The modified alpha power law based model of statistical fluctuation in nanometer FGMOSFET
Published in Cogent Engineering, 2018
The accuracy verification has been performed by comparing to its BSIM4 based reference () obtained by using the Monte-Carlo simulation of the BSIM4 based model of FGMOSFET with 1000 runs by using Simulation Program with Integrated Circuit Emphasis (SPICE). Such BSIM4 based model can be obtained by using the equivalent circuit depicted in Figure 2 with the core MOSFET modelled with BSIM4. For solving the convergence problem, the simulation methodology with SPICE proposed by Ramirez-Angulo, Gonzalez-Altamirano, and Choi (1997) has been adopted.