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Exceptions, interrupts, and input/output systems
Published in Joseph D. Dumas, Computer Architecture, 2016
Almost any instruction set architecture one can think of has some type of trapping instruction. A simple embedded microcontroller, such as the Motorola 68HC12, has only one with the mnemonic SWI (for software interrupt). The ubiquitous Intel x86 architecture defines an INT (interrupt) instruction with an op code followed by an 8-bit vector number for a total of 256 possible software interrupts, each with its own exception vector. (In a given system, some of the vectors will be used for hardware interrupts, so not all 256 INT instructions are typically available for use.) The Motorola 68000 implements 16 unconditional trap instructions, TRAP #0 through TRAP #15. The 68000 also has a conditional trap instruction, TRAPV, which causes a trap only if the overflow flag in the processor’s condition code register (CCR) is set. (The 68020 and subsequent CPUs in that family defined additional TRAPcc instructions that tested other conditions to decide whether or not to cause a trap.) Even a reduced instruction set computer (RISC) architecture, such as SPARC, defines a set of 128 trap instructions (half the total number of exceptions). In each of these architectures, the process for handling traps, including the vectoring/table lookup mechanism for locating the handlers, is essentially identical to that employed for hardware interrupts. The only difference is that instead of a device placing a vector number on the bus, the vector number is generated from the op code of the trapping instruction (or a constant stored immediately following it); thus, the process is more akin to autovectoring.
A Review on Live Memory Acquisition Approaches for Digital Forensics
Published in Mukesh Kumar Awasthi, Ravi Tomar, Maanak Gupta, Mathematical Modeling for Intelligent Systems, 2023
The Intel IA-32 architecture, which supports 32-bit computing, is referred to as x86 architecture. It defines Intel’s 32-bit processors instruction set and programming environment. Byte addressing is used in this architecture, and software running on this processor may have a linear address space of up to 4GB and a physical address space of up to 4GB. Virtual memory, paging, privilege levels, and segmentation are all supported by the IA-32’s operational protected mode.
Fifty years in home computing, the digital computer and its private use(er)s
Published in International Journal of Parallel, Emergent and Distributed Systems, 2020
It seems to be the usability of GUI operating systems that caused this convergence: Microsoft’s Windows, Apple’s Mac OS and some Linux variants with such GUI OS’s were able to divide the market among each other. Even if some companies had tried to compete with alternative concepts (like Transputer and RISC CPUs) Intel’s x86 microprocessor architecture became the standard for PCs bit by bit. (Two decades later Achorn began to reconquer with RISC CPUs for mobile devices.)