China 
Africa 
Explore chapters and articles related to this topic
OFDM-Based VLC Systems FPGA Prototyping
Published in Zabih Ghassemlooy, Luis Nero Alves, Stanislav Zvánovec, Mohammad-Ali Khalighi, Visible Light Communications, 2017
Mónica Figueiredo, Carlos Ribeiro
In October 2013, Xilinx released the last version of their Integrated Synthesis Environment (ISE) Design Suite. It has been discontinued in favor of Vivado, a newly re-architected complete FPGA design suite. While ISE is still available and will be supported indefinitely for customers targeting Virtex-6, Spartan-6, and their previous generations, Vivado must be used for 7-series, Ultrascale and future device families. This section will look into both design suites, as many designs may not require the usage of 7-series or Ultrascale FPGAs and thus, must still resort to ISE tools.
Development of machine tool communication method and its edge middleware for cyber-physical manufacturing systems
Published in International Journal of Computer Integrated Manufacturing, 2023
S M Nahian Al Sunny, Xiaoqing “Frank” Liu, Md Rakib Shahriar
The software tools and programming languages used for the implementation are listed below: Vivado 2018.3: It is Xilinx’s official programming tool and was used for hardware design, developing PL modules in VHDL language, and interconnecting the interfaces of PS and PL.Software Development Kit (SDK): This tool is also provided by Xilinx and was used to define and create device tree, FSBL (First Stage Boot Loader), and Zynq boot image required to run Petalinux OS on PS. It was also used to load these files to the board.Python: This scripting language was used to program, compile, and execute programs for PS modules in Petalinux OS.
Automatic offloading method of loop statements of software to FPGA
Published in International Journal of Parallel, Emergent and Distributed Systems, 2021
For offloading to GPUs, OpenACC only specifies the #pragma acc kernels directive so that specified loop statements can be executed on a GPU or CUDA can describe more detail control. To control an FPGA, OpenCL can be used to describe detailed control similar to using CUDA, and high level synthesis (HLS) tools can specify more abstract control similar to using OpenACC. The following ten description steps are needed for OpenCL. (1. Prepare devices. 2. Prepare kernels. 3. Allocate devices memory. 4. Transfer data from hosts to devices. 5. Configure variables of kernel functions. 6. Execute kernel functions. 7. Transfer data from devices to hosts. 8. Release devices memory. 9. Release kernels. 10. Release other objects such as devices.) Each vendor HLS has a different specification, but it can control an FPGA more abstractly. For example, Xilinx Vivado HLS specifies FPGA processing by #pragma HLS PIPELINE, #pragma HLS UNROLL, and so on, similar to using OpenACC. Intel FPGA SDK for OpenCL recognises not only the OpenCL standard but also other extensions such as #pragma directives.
A hardware intelligent processing accelerator for domestic service robots
Published in Advanced Robotics, 2020
Yutaro Ishida, Takashi Morie, Hakaru Tamukoh
In this experiment, we used a Xilinx XC7Z020 SoC and its evaluation board [26,38]. To synthesize the internal circuit of the FPGA, we utilized a Xilinx Vivado HLS 2016.2, which is a high-level synthesis tool [39]. The synthesis results of feature extraction and machine learning are presented in Table 3. Moreover, the minimum and maximum latency of the internal circuit for one region of interest are 0.257 and 0.565 ms, respectively.