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Field Programmable Gate Arrays
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
SystemC [http://www.systemc.org] is a set of library routines and macros implemented in C++ that allow a hardware designer to specify and simulate hardware processes using a C++ syntax. The benefits of this approach include the ability to use object-oriented coding techniques in development and the use of a standard C++ compiler to produce simulatable executables. Similar to HDLs, SystemC models are specified as a series of modules that connect through ports. In addition, SystemC supports more flexibility in terms of the number of usable data types and the dynamic allocation of memory. A formal specification of SystemC (IEEE1666-2005) was recently accepted, and further developments are in progress. Synthesis tools that allow the translation of SystemC designs into the Electronic Design Interchange Format [EDIF, an industry-standard netlist format (Kahn and Goldman 1992)] are currently available, though the technology is still relatively new.
Design and Verification Languages
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
SystemC can be thought of as a dialect of C++ for modeling digital hardware. Like Verilog and VHDL, it supports hierarchical models whose blocks consist of input/output ports, internal signals, concurrently running imperative processes, and instances of other blocks. The SystemC libraries make two main contributions: an inexpensive mechanism for running many processes concurrently (based on a lightweight thread package; see Liao et al. [36]) and an extensive set of types for modeling hardware systems, including bit vectors and fixed-point numbers. A SystemC model consists of a series of class definitions, each of which define a block. Methods defined for such a class become concurrently running processes, and the constructor for each class starts these processes running by passing them to the simulation kernel. Simulating a SystemC model starts by calling the constructors for all blocks in the design and then invoking the scheduler, which is responsible for executing each of the concurrent processes as needed.
Cycle-Accurate System-Level Modeling and Performance Evaluation
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
Marcello Coppola, Miltos D. Grammatikakis
High-level SystemC-based modeling involves hardware objects as well as system and application software components. For models of complex safety critical systems, software components may include calls to an RTOS model [22]. An RTOS model abstracts a real-time operating system by providing generic system calls for operating system management (RTOS kernel and multitask scheduling initialization), task management (fork, join, create, sleep, activate), event handling (wait, signal, notify), and real-time modeling. SystemC 3.0 is expected to include user-defined scheduling constructs on top of the core SystemC scheduler, providing RTOS features such as thread creation, interrupt, and abort. During software synthesis, an RTOS model may be replaced with a commercial RTOS.
A programmable ternary CPU using hybrid CMOS/memristor circuits
Published in International Journal of Parallel, Emergent and Distributed Systems, 2018
Daniel Wust, Dietmar Fey, Johannes Knödtel
SystemC is chosen for modelling as it allows crucial components of the CPU to be modelled on register-transfer level, whereas components omitted from the performance measurements can be described on a high abstraction level, thus allowing faster simulations runs compared to a model based entirely on register-transfer level. This chapter shows how to model fundamental components of the CPU such as logic gates and the memristor using SystemC.