China
Africa
Explore chapters and articles related to this topic
Special-purpose and future architectures
Published in Joseph D. Dumas, Computer Architecture, 2016
Conventional computers have increased by orders of magnitude in speed over their 70-plus years of existence. Much of this increase in speed and computing power has been made possible by continuing reductions in the sizes of the individual components used in their construction. Vacuum tubes gave way to discrete semiconductor devices, which, in turn, were replaced by integrated circuits. Over the years, the sizes of the individual transistors that make up an integrated circuit have shrunk to the point at which each individual device is a tiny fraction of a micron (more properly known as a micrometer or one millionth of a meter) across. In fact, Intel’s latest microprocessors based on the Broadwell (2014) and Skylake (2015) microarchitectures use 14-nanometer transistors (a nano-meter is one billionth, or 10–9, of a meter). It has been estimated that integrated circuit transistor sizes will shrink to single-digit nanometers by the year 2018 or 2019.
Performance comparison of commonly used photoacoustic tomography reconstruction algorithms under various blurring conditions
Published in Journal of Modern Optics, 2022
The k-Wave toolbox was utilized to compute the PA signals [7]. Figure 1(a) shows the schematic of the simulation setup in 2D. A vasculature phantom as shown in Figure 1(b) was considered in this study. The size of the computational domain was 1101 × 1101 grid points. The length of each pixel was 0.1 mm. An absorbing layer of width 2 mm was placed to wrap the computational domain. A total of 80 detectors (denoted by red solid circles in Figure 1a) were circularly placed over an angle at a distance of 50 mm from the centre of the simulation domain. The size of the imaging region was 20×20 mm (consisting of 201×201 grid points). The density and the speed of sound of the medium were taken as 1000 kg/m and 1500 m/s, respectively. The numerical phantom was loaded occupying the imaging region and then the forward simulation was performed. The PA signals were acquired by the detectors. For each PA signal, pressure data for 2500 time points with an interval of 20 ns were recorded. A 40-dB noise was added to such a signal (using AddNoise function of the k-Wave toolbox). The forward simulation code was executed in a virtual machine (RAM: 256 GB, cores: 80, clock speed: 2.19 GHz, processor: Intel Core (Skylake, IBRS), OS: CentOS). The execution time was about 17 minutes.
Recent EUROfusion Achievements in Support of Computationally Demanding Multiscale Fusion Physics Simulations and Integrated Modeling
Published in Fusion Science and Technology, 2018
I. Voitsekhovitch, R. Hatzky, D. Coster, F. Imbeaux, D. C. McDonald, T. B. Fehér, K. S. Kang, H. Leggate, M. Martone, S. Mochalskyy, X. Sáez, T. Ribeiro, T.-M. Tran, A. Gutierrez-Milla, T. Aniel, D. Figat, L. Fleury, O. Hoenen, J. Hollocombe, D. Kaljun, G. Manduchi, M. Owsiak, V. Pais, B. Palak, M. Plociennik, J. Signoret, C. Vouland, D. Yadykin, F. Robin, F. Iannone, G. Bracco, J. David, A. Maslennikov, J. Noé, E. Rossi, R. Kamendje, S. Heuraux, M. Hölzl, S. D. Pinches, F. Da Silva, D. Tskhakaya
Following the increasing computational needs of first-principle simulations and IM, the growing number of HPC users, success in code optimization, and the ability to scale to a large number of cores, the EU extended its computational capabilities by acquiring a new supercomputer for fusion applications under EUROfusion. This supercomputer, called MARCONI-FUSION, is a dedicated part of a larger supercomputer hosted at the Inter-University Computing Consortium (CINECA) (Bologna) under a EUROfusion Project Implementing Agreement with the National Agency for New Technologies, Energy and Sustainable Economic Development (ENEA)/CINECA. It consists of two parts: a conventional processor part and a many-cores processor part. The first phase of the conventional part [based on Intel Xeon-Broadwell processors for a total peak performance of 1 petaflop (Pflop)] of this machine has been operational since mid-2016 and its replacement in a second phase [5 Pflop of Intel Xeon-Skylake processors] is now in progress. The accelerated part, in production since the beginning of 2017, consists of 1 Pflop of Intel Knights Landing many-cores processors. The purpose of this partition is to offer EUROfusion users, in continuation of the Intel Knight Corner partition of HELIOS, access to compute nodes that are very efficient for highly parallel and well-vectorized codes. The compute nodes are interconnected by an Intel Omni-Path network with a fat-tree topology with bandwidth performances measured by means of the Intel MPI Benchmark (Fig. 1), and are connected to a high-performance general parallel file system (GPFS) storage system. Thanks to the CINECA Tier-0 Development Roadmap of the HPC infrastructure for the period 2015 to 2020, the EU fusion community takes advantage of HPC resources based on the latest technology generation of processors.