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Pipeline Architecture
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
Intel has continuously introduced a number of more modern multicore products using the constantly evolving more advanced VLSI technology to achieve an even higher performance while preserving the backward compatibility to keep up with its family concept. These processors with their standard CISC instruction set have combined RISC design standard techniques, such as micro-operation pipeline, multiple functional units, and out-of-order sequencing, in their internal structure. The original Core brand refers to Intel’s 32-bit mobile dual-core X86 CPUs that were derived from a more enhanced version of the Intel P6 microarchitecture, the Pentium M branded processors. The Core brand comprised two branches: the Duo (dual-core) and Solo (Duo with one disabled core, which replaced the Pentium M brand of single-core mobile processors). It emerged in parallel with the NetBurst microarchitecture (Intel P68) of the Pentium 4 brand and was a precursor to the 64-bit Core microarchitecture of Core 2 branded CPUs.
The PC
Published in Mike Tooley, PC Based Instrumentation and Control, 2013
The latest Pentium 4 architecture is based on new ‘NetBurst’ architecture that combines four technologies: Hyper Pipelined Technology, Rapid Execution Engine, Execution Trace Cache, and a 400 MHz system bus. The Pentium 4 processor (seePhoto 1.7) is available at speeds ranging from 1.70 to 2.80 GHz with system bus speeds of 400 and 533 MHz (the latter delivering a staggering 4.2 GB of data-per-second into and out of the processor). This performance is accomplished through a physical signalling scheme of quad pumping the data transfers over a 133-MHz clocked system bus and a buffering scheme allowing for sustained 533 MHz data transfers.
Price-Performance of Computer Technology
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
The fastest processors are now microprocessors. The latest Pentium 4 processor (in March 2001) has a clock speed of 1.5 GHz. The distance that light travels in one clock cycle at 1.5 GHz (667 ps) is about 20 cm. Electric signals are slower than light. This means that the dimensions that a signal must travel within a clock cycle are very small, and almost certainly must be within a single integrated circuit package to achieve results within a single cycle.
Fuzzy-based optimised subset simulation for reliability analysis of engineering structures
Published in Structure and Infrastructure Engineering, 2019
Andrew Utomi Ebenuwa, Kong Fah Tee
In the computations, for each realisation of fuzzy variables, a total of 106 performance function evaluation counts are required to estimate the reliability of the structure at each bound when using the MCS, while a total of 650 performance function evaluation counts are needed when using the optimised SS approach. This clearly demonstrates the computational efficiency of the proposed method. The computational time for the two methodsis assessed, and in both cases, the expressions are defined in analytical form, which makes the computational process fast. The two techniques have been measured running on a central processing unit (CPU) time using a 1.60 GHz Pentium 4 computer. The computational times required for MCS approach is 281 min, while the proposed method is 264 min. Based on the execution time, the proposed method does not provide any significant advantage.
Two efficient algorithms for constructing almost even approximations of the Pareto front in multi-objective optimization problems
Published in Engineering Optimization, 2019
Azam Dolatnezhadsomarin, Esmaile Khorram
In this section, numerical implementations of HPSC and MSPO are provided in six test problems. These test problems show that the proposed algorithms are able to obtain approximations that cover the whole Pareto front and maintain an almost even distribution of the non-dominated points. Then, their results are compared with the results of the NC, WC, SPO, NSGA-II, DE, MOEA/D-DE and SMS-EMOA algorithms. These algorithms were coded in MATLAB® 2016 and all experiments were implemented on a laptop with a Pentium 4 processor at 2.3 GHz and 4 GB RAM running Windows 7 Home Basic Operating system. HPSC is implemented on bi-objective problems with non-convex, connected and disconnected Pareto fronts. Moreover, the SQP algorithm in the MATLAB fmincon solver is used to solve every SOOP in NC, WC, SPO, HPSC and MSPO. In addition, bi-objective problems are solved by HPSC with , NC with , WC with , and other evolutionary algorithms, including DE, MOEA/D-DE, SMS-EMOA and NSGA-II, with a population of size 100. Also, three-objective problems are solved by MSPO with , NC with , SPO with , and the evolutionary algorithms with a population of size 1000. The stop condition in the evolutionary algorithms for bi-objective problems is when the number of the function evaluations reaches 20,000. In addition, these criteria for the three-objective problems are considered when the number of function evaluations reaches 100,000 or the CPU time is over 9000 s.
Modelling and solving an integrated freight train scheduling and trip planning problem with hazardous materials
Published in International Journal of Rail Transportation, 2021
Omar A. Abuobidalla, Mingyuan Chen, Satyaveer S. Chauhan
The computational experiments were conducted on a 2.6 GHz Pentium 4 on DELL laptop with 16 GB of RAM. For the and heuristic method, we solve the problem giving a 1-h time limit to the solver. For the HTPTD heuristic, we also imposed a time limit of 300 seconds for obtaining a feasible solution and 60 seconds given for the solver to solve the sub-MIP problem.