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Integration of Graphics Processing Cores with Microprocessors
Published in Tomasz Wojcicki, Krzysztof Iniewski, VLSI: Circuits for Emerging Applications, 2017
Deepak C. Sekar, Chinnakrishnan Ballapuram
Ivy Bridge was a 22-nm product from Intel that integrated CPU and GPU cores on the same die [3]. The four x86 CPU cores and graphics core were connected through a ring interconnect and shared the memory controller. Ivy Bridge had 1.4 billion transistors and a die size of about 160 mm2. It was the first product that used a trigate transistor technology.
Integration of Graphics Processing Cores with Microprocessors
Published in Rohit Sharma, Krzysztof Iniewski, Sung Kyu Lim, Design of 3D Integrated Circuits and Systems, 2018
Deepak C. Sekar, Ballapuram Chinnakrishnan
Ivy Bridge was a 22 nm product from Intel that integrated CPU and GPU cores on the same die. The four x86 CPU cores and graphics core were connected through a ring interconnect and shared the memory controller. Ivy Bridge had 1.4 billion transistors and a die size of about 160 mm2. It was the first product that used a trigate transistor technology.
Improving the energy efficiency of data-intensive applications running on clusters
Published in International Journal of Parallel, Emergent and Distributed Systems, 2020
Weifeng Liu, Jie Zhou, Bin Gong, Hongjun Dai, Meng Guo
A module has been designed for the analysis agent by us which abstracts the hardware and allows the agent to be independent from system architectures. The module design follows an inheritance design pattern. For extending the family of supported system architectures, we only need to code a new class to implement the predefined interface which standardises the access to energy information. The analysis agent samples the energy information via the interface with a set frequency. Take Intel Xeon Sandy and Ivy Bridge architecture processor for example, the implementation of the energy profiling interface is based on RAPL. RAPL provides MSRs to give the total amount of energy consumed by power plane 0 (PP0, cores), power plane 1 (PP1, the uncore devices), the package (PKG, the entire socket, PKG = PP0 + PP1), and dram (sum of DIMM energies related to the socket, which is not included in the package power). Moreover, the operating system can also set a energy budget for a certain execution window by RAPL. To meet the energy limitation, processors scale their frequency and voltage.
Speeding Up Monte Carlo Computations by Parallel Processing Using a GPU for Uncertainty Evaluation in accordance with GUM Supplement 2
Published in NCSLI Measure, 2018
C. M. Tsui, Aaron Y. K. Yan, H. W. Lai
Modern CPUs for PCs normally have 2 to 4 cores (e.g. Intel Core i3 and i5). High performance CPUs may have up to 6 (e.g., Intel Core i7-8700) or 8 cores (e.g., AMD Ryzen 7). In contrast, GPUs have hundreds or even thousands of cores. Each core is capable of handling one or more floating point operations per clock cycle. The features of some typical GPUs are given in Table 1. GPUs from Nvidia or AMD are usually packaged as expansion cards in a PC. On the other hand, all the Intel Core processors since the third generation (code name Ivy Bridge) include integrated GPUs (called Intel HD Graphics) capable of running OpenCL applications. The Intel integrated GPUs have lower performance than the discrete solutions from Nvidia and AMD. But they come at no extra cost and still offer respectable processing power.
Approximation algorithms in partitioning real-time tasks with replications
Published in International Journal of Parallel, Emergent and Distributed Systems, 2018
Jian (Denny) Lin, Albert M. K. Cheng, Gokhan Gercek
The employing of multiple processing units has become a standard framework that is widely adopted in modern computing environment to accommodate the increasing computational demand of computing intensive applications. From smart phones/PCs/Laptops to servers and supercomputers, multiprocessor systems lead us entering into an era where they play a major role. While today the Intel Xeon family provides up to 18 cores in its products, one of the fastest supercomputers Tianhe-2 runs 16,000 computer nodes, each comprising two Intel Ivy Bridge Xeon processors and three Xeon Phi coprocessor chips. These systems greatly improve performance and cost-efficiency of computation in different fields. At the same time, they draw research attentions to solve a variety of specific problems of using them. In this paper, we generalise a system with multiple processing units, including a multi-core system or a system running multiple processors, as a multiprocessor system.