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Metal Oxide Semiconductor High Electron Mobility Transistors
Published in D. Nirmal, J. Ajayan, Handbook for III-V High Electron Mobility Transistor Technologies, 2019
D. K. Panda, G. Amarnath, T. R. Lenka
Also, these GaN-based MOS-HEMTs have been considered to be the prime choice in order to realize superior performance in high power amplifiers (HPAs) designs. Recently, these HPAs have become essential for wider bandwidth operation and high linearity operations at lower power consumption. While LDMOS or HEMT have initially been broadly used as high-power amplifier devices, MOS-HEMT provides the following advantages. First, higher power-added efficiency (PAE), which saves electrical power consumption and reduce the cost and size of HPAs due to the small amount of heat dissipation. Next, high operating voltage, MOS-HEMT operates at higher supply voltage similar to power feeder voltage range which is generally used for radar and satellite communication equipment. Generally, the design of amplifier becomes more critical as the low device impedances. GaN-based MOS-HEMTs show higher impedance than different devices. Thus, the HPA designers can utilize the advantages of MOS-HEMTs to increase the performance of HPAs with wide coverage of frequency bands and higher PAE with respect to the required HPA performance.
MOSFETs for RF Applications
Published in Frank Schwierz, Hei Wong, Juin J Liou, Nanometer CMOS, 2010
Frank Schwierz, Hei Wong, Juin J Liou
In power amplifiers where heat dissipation or battery power is of concern, the power-added efficiency PAE becomes an important figure of merit. It is defined by () PAE=Pout(rf)−Pin(rf)Pin(dc)
Power Amplifier Principles and Modern Design Techniques
Published in Krzysztof Iniewski, Wireless Technologies, 2017
PE is the power conversion efficiency reflecting the percentage of the DC power drawn from the power supply, which has been converted into output signal power. This figure of merit is also called drain/collector efficiency. Power-added efficiency (PAE) is calculated by subtracting the input power from the output power to include the effect of the PA driver in the efficiency metric. Obviously, for large power gains, PAE approaches power efficiency (PE).
High linear low voltage CMOS power amplifier for 2.4 GHz applications
Published in International Journal of Electronics Letters, 2023
S Manjula, P Anandan, M Suganthy
Chee et al. designed a class AB power amplifier which used the single stage cascode structure which is operated at a supply voltage of 1.2 V. At 1.92 GHz frequency, this amplifier was achieved 35% drain efficiency and 2.6 mW output power (Chee et al. (2004). Shao et al. presented the single stage differential class AB power amplifier which has three parallel cascade of cascode structure. It achieved PAE of 25.34% and consumed 22 mW at 1.2 V supply (Shao et al. (2010)). Generally, the differential cascode structure increased the power consumption. A two-stage driver amplifier for the unlicensed 2.4 GHz band was described by Le et al. (2011). The cascode amplifier was designed as the first stage, and the current reuse output stage was designed to reduce DC current as shown in Figure 2(b). In class A mode, the driver amplifier was biased. It achieved 16 dB gain, 31% drain efficiency, 20% PAE, and 8.1 mW dc power consumption in order to reach 3 dBm transmit power. Chenjian et al. (2013) built a Class AB power amplifier for a 2.4–2.4835 GHz Wireless Sensor Network (WSN) system using 0.18 m CMOS technology. At 6.35dBm output power and 15.3 mW power consumption from1V supply voltage, this PA had a power added efficiency (PAE) of 26.73%. The existing linear PAs still require high dc power to achieve output power. Power amplifiers with low power consumption and great efficiency are a difficult problem to design. The design of low power linear PA is necessary for achieving the desired output power with good efficiency. In this work, a linear class AB power amplifiers are proposed to work under low supply voltage and low dc power for achieving 0 dBm output power.
A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications
Published in International Journal of Electronics, 2023
Dušan P. Krčum, Đorđe P. Glavonjić, Veljko R. Mihajlović, Lazar V. Saranovac, Vladimir M. Milovanović, Ivan M. Milosavljević
Large signal parameters of the designed power amplifier are presented in Figure 12. Delivered saturated output power at extracted netlist simulation is typically 12 dBm, while OP1dB is in the order of 7 dBm at 61 GHz. Peak power-added efficiency (PAE) occurs for 2-dBm input power level and equals 15%. Large signal parameters of the complete TX chain are also verified for the entire frequency range, and the main results are presented in Figure 13. It is shown that saturated output power is constant over the 7-GHz bandwidth, while peak PAE and OP1dB roll-off at higher frequencies are equal to 12% and slightly below 5 dBm, respectively.
Design and implementation of 75~110 GHz elliptical dual balun in 90 nm CMOS for W-Band transceiver
Published in International Journal of Electronics, 2019
Thanks to the swift evolution of CMOS technology (Lin et al., 2010), now it is widely used to implement radio-frequency integrated circuits (RFICs) for millimeter-wave (MMW) communication systems, such as 77 GHz automotive radars (Lin, Wen, & Wang, 2014), 94 GHz imaging radars (Lin, Lan, Wang, Chi, & Lu, 2016), and 210 GHz chip-to-chip communication (Moghadami, Hajilou, Agrawal, & Ardalan, 2015). In transmitter design, power amplifier (PA) is a key component which amplifies the up-converted (or modulated) IF signals to the requested power level over the RF band of interest. To meet the output power (Pout) specification of PAs, multi-way architecture is usually adopted (Law & Pham, 2010; Lin & Nguyen, 2017). In multi-way PA, power splitter and combiner are commonly used (Boccia, Emanuele, Shamsafar, Amieri, and Amendola 2015; Babu, Singh, & Jha, 2005). The basic requirements of a PA include fine impedance matching at the input and output ports, high power gain, high Pout and linearity, and high power-added efficiency (PAE) over the operation band. Figure 1(a) shows the block diagram of a conventional four-way PA for achieving high Pout (Law & Pham, 2010). The PA unit is normally a three-stage cascaded amplifier, which includes input, driving and output stages (see Figure 2(b)). In addition, a four-way Wilkinson power splitter, which is composed of three two-way Wilkinson power splitters (Hawatmeh, Shamaileh, Dib, & Sheta, 2013; Hazeri, 2012), is needed to averagely split the input signals into four ways. A four- way Wilkinson power combiner, which is composed of three two-way Wilkinson power combiners, is required for combining the amplified signals by the four PA units into a single output. For comparison, a W-band four-way Wilkinson power splitter is designed. Its chip size is 0.35 mm× 0.5 mm (i.e. 0.175 mm2), as shown in Figure 1(b). The large chip size (i.e. long transmission line (TL)) of the four-way Wilkinson power splitter and combiner in the PA normally leads to ungratified Pout and PAE.