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Computer and Internet Reliability
Published in B.S. Dhillon, Applied Reliability, Usability, and Quality for Engineers, 2023
In this case, three identical units/modules perform the same task simultaneously and the voter compares their outputs (i.e., the units/modules) and sides with the majority [3, 17]. More specifically, the TMR system fails only when more than one unit/module malfunctions or the voter malfunctions. In other words, the TMR system can tolerate failure of a single unit/module. An important example of the TMR scheme application was the SATURN launch vehicle computer, which used TMR with voters in the central processor and duplication in the main memory [20]. The TMR scheme's block diagram is shown in Fig. 7.2 and the blocks in the diagram represent units/modules and the voter. In addition, the TMR system without the voter is inside the dotted rectangle.
Overview of the NASA ETDP RHESE Program
Published in John D. Cressler, H. Alan Mantooth, Extreme Environment Electronics, 2017
Beyond RHBA, the next level of hardening electronic components is referred to as radiation hardening by design (RHBD). RHBD implies that an electronic part or board has been radiation-hardened by virtue of the component layout and circuit architecture of on-chip gates, devices, and interconnects independent of any special fabrication process or technique. Examples of RHBD techniques include using TMR strategies within the chip layout, designing dopant wells and isolation trenches into the circuit layouts, implementing error detecting and correction circuits [16], and using device spacing and decoupling design rules. Disadvantages to these techniques include the extra devices required to implement TMR, the extra power load these devices consume, and the extra chip area required to isolate devices, gates, and latches.
Transition Metal Oxide-Based Multiferroic Materials for Spintronics and Energy-Harvesting Applications
Published in Vijay B. Pawade, Paresh H. Salame, Bharat A. Bhanvase, Multifunctional Nanostructured Metal Oxides for Energy Harvesting and Storage Devices, 2020
Here, we will mostly explore multiferroic materials that may not or may have direct ME coupling between them. The magnetic state of the system can be altered, and it can be characterized in many ways as depicted by Fusil et al. [10]. They can be classified into four types: TMR, GMR, AMR, and MR. Amongst these, TMR has gained interest recently due to low power consumption, high density, and multiple memory states that can be achieved. Also, this can be used for sensing applications. Here, we will first focus on the multiferroic materials used in the multiferroic tunnel junctions (called MFTJ). In multiferroic, single-phase multiferroic materials, as well as a layer of the ferroelectric and ferromagnetic layer, have been used.
Review of Approaches for Radiation Hardened Combinational Logic in CMOS Silicon Technology
Published in IETE Technical Review, 2018
Vaibhav Sharma, Arvind Rajawat
As gates are combined to form a combinational logic block consisting of number of gates, it is not efficient to harden each and every gate. Hence, we revised a number of approaches which could be utilized to harden combinational logic as a whole. Popular and simple approaches involve implementation of redundancy approaches, such as, triple modular redundancy (TMR) which constitutes of three copies of original circuit (with outputs O1, O2, O3) followed by a voter circuit. The outputs (O1, O2, O3) are fed as inputs to the voter circuit, which is designed in such a way that it pass that logic as the primary output which is in majority at its inputs. However, the assumption is that only one output of the three copies is affected due to radiation. A modification of TMR for lowering the power and area overhead is dual modular redundant (DMR) approach. DMR uses two copies of original circuit and a comparator. This approach is suitable for error detection but not as useful for error recovery. These approaches no doubt involves a high cost overhead, albeit much desirable for space applications. New logic level approaches generally constitutes of a design part for gates and an adopted algorithm for a way to implement the design part.
A Review on SEU Mitigation Techniques for FPGA Configuration Memory
Published in IETE Technical Review, 2018
T. S. Nidhin, Anindya Bhattacharyya, R. P. Behera, T. Jayanthi
One of the techniques proposed is for detecting and repairing SEUs within configuration memory of Xilinx Virtex-4 FPGA using the ICAP interface (error injection and scrubbing). TMR was applied to the ICAP scrubber to make it more dependable. A special implementation of TMR that uses voters on the feedback loops within the circuit. Feedback TMR reduces the risk of the next state of a calculation error by reducing the number of single point failure. Since the ICAP scrubber uses many state machines to control the data between key components, a feedback TMR implementation made it more dependable circuit. ICAP and frame ECC cannot be triplicated because these are not enough resources to apply triplication [55]. Table 2 depicts the benefits and drawbacks of the major scrubbing methods. It is categorised based on the complexity of implementation and the error mitigation efficiency and quantified as low, medium, and high.
Analyzing phased-mission industrial network systems with multiple ordered performance levels
Published in Journal of Industrial and Production Engineering, 2019
Yu-Huan Gong, Yu-Chang Mo, Yu Liu, Yi Ding
The data gathering nodes in each cluster have two working configurations. Three nodes can work in a parallel configuration or in a triple modular redundancy (TMR) configuration. TMR is a fault tolerant form of N-modular redundancy, in which three nodes perform a process and that result is voted to produce a single output. If any one of the three nodes fails, the other two nodes can correct and mask the fault.