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Forward Error Correction Coding
Published in Jerry D. Gibson, The Communications Handbook, 2018
Vijay K. Bhargava, Ivan J. Fair
Some subclasses of these codes are of special interest. Hamming codes are perfect single error correcting binary BCH codes. Full length Hamming codes have n = 2m - 1 and k = n - m for any m greater than two. The duals of these codes are maximal-length codes, with n = 2m - 1, k = m, and dmin = 2m-1. All 2m - 1 non-zero code vectors in these codes are cyclic shifts of a single non-zero code vector. ReedSolomon (RS) codes are non-binary BCH codes defined over GF(q), where q is often taken as a power of two so that symbols can be represented by a sequence of bits. In these cases, correction of even a single symbol allows for correction of a burst of bit errors. The block length is n = q - 1, and the minimum distance dmin = 2t + 1 is achieved using only 2t parity symbols. Since RS codes meet the Singleton bound of dmin < n - k + 1, they have the largest possible minimum distance for these values of n and k and are called maximum distance separable codes.
Coding
Published in Goff Hill, The Cable and Telecommunications Professionals' Reference, 2012
In practice, however, the decoder should be modified because errors cannot occur in untransmitted bits. Consider a shortened Hamming code. The Hamming code can normally correct any single error. However, if on receiving a shortened codeword the decoder calculates a syndrome that would normally imply an error in one of the untransmitted bits, that cannot be the true cause. The next most likely cause is a double-error pattern in the transmitted bits. If there were only one double-bit error pattern that could produce that syndrome, the decoder could apply the corresponding double-bit correction. If, however, more than one double-bit error pattern could have produced that syndrome, the decoder cannot guarantee to correct the error.
Computer Engineering
Published in Arun G. Phadke, Handbook of Electrical Engineering Calculations, 2018
Peter Athanas, Yosef Tirat-Gefen
The Hamming code is a self-correcting code that can detect and correct a single error. To accomplish both error detection and error correction, additional redundant data bits are appended to each transmitted word. At the receiver end, the redundant bits are used to determine whether an error has occurred (whether any one of the bits in the received word has flipped). If so, the redundant data can be used to determine which bit is faulty. Once determined, the faulty bit can be corrected and the word restored to its original transmitted state. The first step in this process is referred to as error detection, and the second is referred to as error correction.
A Review on SEU Mitigation Techniques for FPGA Configuration Memory
Published in IETE Technical Review, 2018
T. S. Nidhin, Anindya Bhattacharyya, R. P. Behera, T. Jayanthi
The most dependable approach to SEUs detection and correction in memory cells is based on ECCs. An encoder is required before writing into the memory and decodes the bits when read. The encoding and decoding latency affect the performance of the system, so most of the applications prefer the codes which have a simple decoding process. Single error correction (SEC) Hamming codes [30] are the most commonly used and it can detect and correct single bit error. PR combined with error correcting code can be used for SEU mitigation in the configuration memory. The error recovery mechanism depicted in [31] consists of ICAP device, frame ECC device, dual-port block RAM, and control logic. A basic block diagram of the error recovery mechanism is shown in Figure 1. The error recovery mechanism uses the ICAP to read and write a configuration frame. The frame ECC device is used to detect and locate errors inside the FPGA configuration frame, it works in parallel with the ICAP device. While the ICAP device reads the particular frame, the frame ECC uses the frame data to compute the syndrome value. The internal block RAM is used to store the configuration commands and to buffer the frame data during the error correction. The control logic manages the error detection and correction process. The controller is composed of a finite state machine, frame address counter, and error detection logic. The error detection logic determines the location of a single error within the frame. In this recovery mechanism, a SEC double error detection (DED) Hamming codes is used [32]. If there are two errors it can only detect but cannot correct so the recovery mechanism will be stopped and the double error is reported. This mechanism cannot be used for more than two errors.
Implementation of Novel Block and Convolutional Encoding Circuit Using FS-GDI
Published in IETE Journal of Research, 2023
Mohsen A. M. El-Bendary, O. Al-Badry, A. E. Abou-El. Azm
Hamming codes are error control schemes; these codes can correct single-bit errors and detect two errors. It is widely used in various applications such as satellites and computer networks [33]. Hamming codes have been implemented in Ref. [34], using CMOS logic circuit in 250 nm technology node with 3 and 5 parity bits. Tanner EDA tool is utilized for implementing and testing these Hamming codes. Simulation experiments of these presented Hamming codes showed that, codes with check-bits = 3 consumed power 4.75e−4 (W) and 5.17e−3 for 5 parity bits, while the delay was 8.82e−10 (S) for 3 bits and 4.90e−8 (S) for 5 bits.
Trinity by the Numbers: The Computing Effort that Made Trinity Possible
Published in Nuclear Technology, 2021
Remaining in Los Alamos for 6 months after the war to help compile a technical description of the Lab’s punched-card operation, Hamming then went to Bell Labs. Sharing an office with Claude Shannon, often called “the father of information theory,” Hamming was involved in nearly all of Bell Labs’ most prominent achievements in computer engineering over the next 15 years, including the error-correcting “Hamming” codes that bear his name today.41,44