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Manufacturing Test
Published in Jack Arabian, Computer Integrated Electronics Manufacturing and Testing, 2020
Built-in self test (BIST) is probably the most sophisticated and advanced form of testing. In addition to solving the complexity of the probing problem, BIST contributes to the reduction of cost for automatic test equipment (ATE) to test advanced electronics products. BIST incorporates circuitry within the product to monitor the integrity of its functionality. The BIST circuitry is powered up and operated with the rest of the circuit of the product to electrically “exercise” the product with predetermined input test vectors. These vectors are designed (usually in terms of zeros and ones) to set, reset, toggle, clear, enable, and disable portions of a circuit in a specified sequence with an expected output. If the actual output matches the expected pattern (usually stored in a memory circuit onboard) the circuit is declared as “good.” If, however, the output has a discrepancy, the built-in test circuit will flag it by lighting a red light, sounding an audio alarm, activating a printed display message, or, in cases of safety, shutting down the operation of the circuit.
Circuit-Level Testing
Published in Santanu Chattopadhyay, Thermal-Aware Testing of Digital VLSI Circuits and Systems, 2018
Built-In Self Test (BIST) is a test methodology in which the test pattern generator and response compactor are integrated with the circuit under test. Typically, a linear feedback shift register (LFSR) is used as the pseudo-random pattern generator, while a multiple input signature register (MISR) is used as the response compactor. After the completion of the test session, the signature obtained in the MISR is shifted out and compared with the stored response. However, to obtain reasonably high fault coverage with pseudo-random patterns, long test sequences often are required. This leads to higher power consumption of the circuit and, consequently, an increase in the peak temperature.
Introduction
Published in Vlad P. Shmerko, Svetlana N. Yanushkevich, Sergey Edward Lyshevski, Computer Arithmetics for Nanoelectronics, 2018
Vlad P. Shmerko, Svetlana N. Yanushkevich, Sergey Edward Lyshevski
Built-in self-test technique (BIST) is a testing technique, in which external test resources are not required to apply test patterns and check a logic network's response to those patterns. In BIST techniques, the test patterns are preliminary loaded into the network or generated by the network itself. A BIST design approach is given in Figure 18.17. There are three main components: the logic network under test, stimulus generator, and response analyzer.
An overview of self-engineering systems
Published in Journal of Engineering Design, 2021
Electronics component designers have, for a long time, exploited the ability of reconfiguration and redundancy to make fault-tolerant systems. One of the early solutions (from the 1980s) is a field-programmable gate array (FPGA), which contains programmable logic blocks and memory elements which can be reconfigured when needed. FPGAs offer a cheaper solution than having a complete redundant system which can quickly lead to spiralling costs (Frei et al. 2013). FPGAs and other evolvable hardware have been extensively researched by previous authors (Zhang et al. 2016). Other authors repaired random access memory (RAM) devices with reconfiguration; faulty memory cells are identified using a memory test (monitoring storage and change of data in cells), data in a faulty memory cell is stored at new spare addresses and the system self-reconfigures to adapt to the change (Nair and Bonifus 2018; Shvydun and Adham 2014). The repair ability of these systems is limited by the availability of redundant parts. Diagnosing faulty cells can be difficult in a complex system, a Built-in Self-testing (BIST) system is often used in electronics to identify faulty cells or parts (Bell et al. 2013).
Memory-Efficient LFSR Encoding and Weightage Driven Bit Transition for Improved Fault Coverage
Published in IETE Journal of Research, 2023
In recent years due to the inventions of complex digital systems and package technologies make testing a difficult task to accomplish, which requires new techniques and solutions Built In Self Test (BIST) [1]. Although BIST is a method for detecting faults within a chip, it must also meet design requirements such as excessive power dissipation during testing, which could result in chip destruction, and memory and resource requirements for incorporating the testing feature, which will increase hardware complexity. In general, a Test Pattern Generator (TPG) is considered as the core unit for implementing BIST which generates a sequence of test patterns to the Circuit Under Test (CUT).
A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process
Published in International Journal of Electronics Letters, 2023
Chua-Chin Wang, Lean Karlo S. Tolentino, Uday Kiran Naidu Ekkurthi, Pang-Yen Lou, Sivaperumal Sampath
Because built-in self-test (BIST), an essential requirement for testability, supports a wider variety of low-power applications, most digital systems utilise the BIST for internal testing. An 8-bit reversible linear phase shift register was developed by Kumar et al. (2017) that reduced the power consumption of the standard LFSR by 10%. An 8-bit LFSR with a weighted random test pattern generator was presented by Bagalkoti et al. (2019) to enhance overall performance, which results in a decrease in time delay but has a trade-off of higher power consumption. Meanwhile, a 256-bit shift register that uses bi-enabled pulse latches was developed by Authimuthu et al. (2022) to replace the commonly-used flip-flops. However, it is implemented using a legacy process (180 nm CMOS) and a higher supply voltage (1.8 V). Another shift register was designed by Jeon (2020) based on quantum-dot cellular automata (QCA) and electronic correlations. It demonstrated high efficiency regarding energy dissipation, time complexity, and optimised area & latency. Compared to using logical effort analysis, the power & area efficiencies and power-delay product (PDP) were optimised in two DETFFs using elephant herding optimisation (EHO) (Sabu & Batri, 2020a, 2020b) and interior search (ISA) & gravitational search (GSA) algorithms (Singh et al., 2018). However, these designs were only proven by simulation results (Jeon, 2020; Sabu & Batri, 2020a,b; Singh et al., 2018). Previously, we presented and designed an 8-bit shift register using DETFF (Ekkurthi et al., 2021). The proposed DETFF design underwent post-layout simulations only, so there was no theoretical analysis or chip measurement. For all of the above concerns to be addressed, a DETFF-based 8-bit shift register fabricated and tested on silicon is presented in this paper to minimise the delay and reduce the power consumption simultaneously.