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Desktop Publishing
Published in Paul W. Ross, The Handbook of Software for Engineers and Scientists, 2018
To describe the thin space you must, once again, realize that artists, not physicists, are behind the scenes. The thin space, by definition, is either 1/3 or 1/4 of an em space. It can vary, but rarely does, within these two bounds. The thin space also defines the width of the typeset numerals zero through nine, plus several other number-type characters (the plus sign, minus or dash, dollar symbol, etc.). In some fonts these characters are thicker than in other fonts (accounting for the variability of the thin space). For most fonts, the thin space width is also the same as the spaceband (ragged, unadjusted word-space use) width.
Inverse Problem Approach Applied to the Study of Heat Transfer Maximization: shape Optimization of Butterfly Inserts
Published in Heat Transfer Engineering, 2023
Luca Cattani, Fabio Bozzoli, Sara Rainieri
Figures 13 and 14 clearly show the distortion in the velocity and temperature profiles produced by all the three geometries thus inducing an uneven q distribution along the circumference. For the two cases of traditional and swirled devices this significantly variable distribution could be ascribed to the generation of a horseshoe vortex ahead of the wings, that justifies the area of enhanced heat transfer. Additionally, the insert generates an extremely thin space among the wings and tube surface; in this region, the fluid is nearly immobile, causing very low heat transfer rate. The maximum values of the pipe surface temperature and the subsequent lowest values of heat flux are achieved close to the wings’ tip (i.e., α ≈ 4π/5 and α ≈ 9π/5), where there is contact among the insert and the tube surface. The fluid flow is brought to stop at this point with an associated increase in pressure as it happens in case of external flow on a sphere or a cross cylinder [26] from this stagnation point the pressure declines with the rising of the longitudinal coordinate and a boundary layer develops in the part of fluid adjacent to the insert wall in the indention part.
Compact, backdrivable, and efficient design of linear electro-hydrostatic actuator module
Published in Advanced Robotics, 2022
Mitsuo Komagata, Ko Yamamoto, Yoshihiko Nakamura
Since accurate machining of microns meter order is difficult, we adopted accurate standard bearing balls and plating. Figure 10(d) shows the designed structure. Widths of gap A and B (, ) can be obtained by the following equations using parameters in Figure 10(e). According to ISO3290 international standard2, G3 graded bearing balls with the diameter of 1 mm can be chosen from the gauge interval of 0.5 . Therefore, diameter of the bearing balls (d) is accurate. The thickness of a middle casing (a) and the thickness of a plate (c) was paid a special attention. Electroless nickel plating for final adjustment is applied to add the thickness at 1 order by controlling plating time. Additionally, in terms of size, this structure plays a role of a thrust bearing with 1 mm thick in thin space. Therefore, miniaturization of the pump can be also expected.
Modeling and Fabrication Aspects of Cu- and Carbon Nanotube-Based Through-Silicon Vias
Published in IETE Journal of Research, 2021
Tanu Goyal, Manoj Kumar Majumder, Brajesh Kumar Kaushik
As technology headway towards more than Moore’s law, there is an immense growth in the need of heterogeneous integration of technologies into the chip cube. Thus, for this increasing drive of integration of disparate signals, i.e. analog, digital, and RF signals and system on chips, Silicon on insulator, SiGe HBTs, GaAs planar ICs, or 2D planar ICs are not suitable [1,2]. The problem with 2D ICs is the long interconnections, physical limits, processing complexity, and higher fabrication cost [3]. This has led to the 3D integration of IC. 3D integration has become prominent for continuous miniaturization in accordance with Moore’s law. In 2D integration, the power and clock signals required to travel around the whole chip thus deteriorates power dissipation and transmission delay. On the other hand, 3D integration provides vertical interconnects that reduce the overall chip area thus optimizing power dissipation and transmission delay of chip and improving packaging density. Different 3D packaging techniques include embedded pattern, active power substrate pattern, and stacked pattern that are realized using basic approaches of pattern packaging. 3D technology enables various functions in ultra-thin space and stacking of disparate packages altogether. General stacking techniques are Die-to-Die, Die-To-Wafer, and Wafer To-Wafer stacking. Die-to-Die approach can be used for dissimilar or same size of dies and known as good dies (KGD) but prone to low throughput problems. On the other hand, die to wafer utilizes wafer-level processes to ameliorate throughput still electrostatic discharge (ESD) and accuracy of placements are issues that have to be resolved. Wafer-to-wafer approach offers high throughputs and reliability with the advantage of being lower cost-effective factor. The major setback of these dies is low yield that is due to the lack of known good dies and inferior flexibility of fabrication. However, wafer-to-wafer technology has major chances to be emerged out as the most promising stacking technology for 3D integration [3].