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Self-Driven Clock Gating Technique for Dynamic Power Reduction of High-Speed Complex Systems
Published in Durgesh Nandan, Basant K. Mohanty, Sanjeev Kumar, Rajeev Kumar Arya, VLSI Architecture for Signal, Speech, and Image Processing, 2023
Roopa R. Kulkarni, S. Y. Kulkarni
One of the predominantly used technique to reduce the unwanted switching of the clock input signal is clock gating. This technique can be employed at all levels of the design namely: system, architecture block, and logic design. In Ref. [8], the authors describe the existing clock gating techniques that is, clock gated positive latch, data driven clock gating and auto gated flip-flops. Each of these have the drawback of either the flip-flop overhead, or short time window or the timing constraint imposed. To overcome, these drawbacks a look ahead clock gating technique is proposed which computes the clock enabling signal of each flip-flop, one cycle ahead of time, depending on the present input cycle. This technique is applied to 4, 8, 16, 32, and 64-bit linear feedback shift register (LFSR). LFSR is the well-known and most commonly used pseudo-random number generator circuit used in the built-in self-test, signature analysis and in spread spectrum communication. The results have shown, an average of power saved is in the range of 27.8% to 42.21% depending on the n-bit of the LFSR.
Practical Constructions of Symmetric-Key Primitives
Published in Jonathan Katz, Yehuda Lindell, Introduction to Modern Cryptography, 2020
A degree-n LFSR will eventually repeat some previous state; once it does, it will then repeatedly cycle among some set of states, and the bits it outputs will begin repeating as well. This corresponds to being in a cycle of the transition graph. The LFSR is maximum length if it cycles through all 2n − 1 nonzero states before repeating; i.e., its transition graph contains a cycle through all 2n − 1 nonzero states. (In the transition graph for any LFSR, the all-0 state has a self-loop. If the all-0 state is ever reached the LFSR remains in that state forever.) If an LFSR is maximum length then, when initialized in any nonzero state, it will cycle through all 2n − 1 nonzero states. Whether an LFSR is maximum length depends only on its feedback coefficients. It is well understood how to set the feedback coefficients so as to obtain a maximum-length LFSR, although the details are beyond the scope of this book.
Symmetric Algorithms I
Published in Khaleel Ahmad, M. N. Doja, Nur Izura Udzir, Manu Pratap Singh, Emerging Security Algorithms and Techniques, 2019
Faheem Syeed Masoodi, Mohammad Ubaidullah Bokhari
In stream cipher design, LFSRs have received a wide acknowledgment primarily due to their inherited characteristics including extensive period, desired statistical properties, and low implementation costs (Masoodi, Alam, & Bokhari, 2012). An LFSR is a shift register that consists of multiple cascaded storage units (flip-flops) and using feedback, cycles the bits on each clock tick. The aim is to iteratively generate a sequence of pseudorandom numbers by performing exclusive-OR (or exclusive-NOR) operation on chosen bits (taps) and blend them with input. An LFSR is said to have generated a maximal sequence (m-sequence), if it can generate every possible unique value (precluding an all 0’s state in exclusive-OR and an all 1’s state in exclusive-NOR) before arriving at its starting state.
Suppression of EMI Using Cost-Effective FPGA-Based Digital Communication Modulation Techniques in Power Converters
Published in IETE Journal of Research, 2023
The binary pattern of the modulating signal is produced by an LFSR (Linear Feedback Shift Register). Using a scheme of a lookup table, the direct digital synthesizer (DDS) generates reference sinusoidal signal. A digital integrator along with the lookup table gives the phase-shifted output waveform. The modulating signal thus obtained is multiplied with the high-frequency carrier signal. It is then compared with a reference sinusoidal signal to produce the firing pulses for the three phases of the rectifier. The modulation techniques thus formulated using VHDL in ISE XILINX platform are then simulated using Model-Sim. The SPARTAN 3E FPGA functions at 20 MHz clock frequency. So, the required switching frequency of 10 kHz with a sampling rate of 50 ns is easily obtained. This leads to a bandwidth of the DSSS with a spread factor of 2000.
Conducted Electromagnetic Interference Spectral Peak Mitigation in Luo-Converter Using FPGA-Based Chaotic PWM Technique
Published in Electric Power Components and Systems, 2019
Sudhakar Natarajan, Pydikalva Padmavathi, Jyotheeswara Reddy Kalvakurthi, Thanikanti Sudhakar Babu, Vigna K. Ramachandaramurthy, Sanjeevikumar Padmanaban
Random switching pulses can be generated with the help of linear feedback shift register (LFSR) which works on the principle of pseudo-random number generation. LFSR is a group of shift registers which use linear functions as a feedback mechanism to modify itself on each rising edge of the clock [19, 20] which is shown in Figure 5. Here logic gates like XOR and XNOR gates are used as linear function to feedback the output bit to input bit. The input given at initial stage is called as “seed.” The bit positions, where next state is affected by linear functions are called as “taps.” The right most bit is the output bit. LFSR can produce maximum 2n − 1 random numbers (except all 0), where n is the number of registers used. Since sequence generated is deterministic and finite, it can repeat the same stream of values from the initial stage until LFSR is clocked. Its output is presented in the form of 1’s and 0’s.
Low spur frequency synthesiser using randomly shifted reference spur to higher frequencies
Published in International Journal of Electronics, 2020
Sakineh Jahangirzadeh, Amir Amirabadi, Ali Farrokhi
The LFSR is used to generate a pseudo-random sequence. The maximum length of an LFSR sequence is. The block diagram of a 4-bit LFSR is shown in Figure 6. The LFSR is composed of four D flip flops and one XOR gate which provides a pseudo-random sequence. It provides random selection between and frequencies for the VTC.