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Combinational logic circuits
Published in David Crecraft, David Gorham, electronics, 2018
The Karnaugh map is a convenient method of representing a logic problem that enables simplifications to be more easily spotted. Some of the important points to remember are: Each square in the Karnaugh map corresponds to a line in the truth table.The coordinates of a square that contains a 1 correspond to a minterm in a Boolean expression.A rectangular cluster of squares corresponds to a product term in a simplified Boolean expression.Coordinates around a Karnaugh map are arranged so that only one variable at a time changes between adjacent columns.Edges and corners ‘wrap around’ to behave as if they were complete groups.Don’t-care terms can be assigned a value to make up a complete group. An inverted map in which the 0s are grouped may give a simpler answer than the conventional map in which 1s are grouped.
The design of combinational logic circuits
Published in J. R. Gibson, Electronic Logic Circuits, 2013
The aim of logic expression minimization was to reduce the circuit complexity and cost. ‘Don’t cares’ can be used to assist in minimization by choosing the circuit outputs in ‘don’t care’ cases to have the values which give the most simple circuit. When ‘don’t cares’ are used in this way they must be indicated in the truth table and on the Karnaugh map by some symbol; the letter X is used here. The minimization technique itself is modified by choosing a ‘don’t care’ condition to give an output of 1 when this reduces the final logic expression and to give an output of 0 in all other cases. The rules for Karnaugh map minimization remain the same with the additional requirement that Xs are to be included in groups of 1s when this increases the group size or reduces the number of groups, the Xs must not be included in groups in other cases. Thus all the 1s must be included in groups but the inclusion of Xs depends on their position relative to 1s.
Mapping Boolean Expressions
Published in Eugene D. Fabricius, Modern Digital Design and Switching Theory, 2017
The graphic approach requires the identification of a minimum number of terms which can represent a given function. In an SOP expression, each of the product terms is called an implicant of the function because it implies the function; i.e., if the product term is true then the function is true. Simplification of a function involves finding the set of prime implicants (implicants which do not imply any other implicants) of the function. In terms of Karnaugh maps, a prime implicant is the largest correct grouping of minterms or maxterms. Any given switching function has one unique set of prime implicants since the set is derived from a unique set of minterms.
Energy-Efficient approximate compressor design for error-resilient digital signal processing
Published in International Journal of Electronics, 2023
Amin Avan, MohammadReza Taheri, Mohammad Hossein Moaiyeri, Keivan Navi
Proposing an Error Correction Module (ECM) is reasonable to achieve a functional multiplier with the proposed (4,2) compressor to obtain more accurate results (Kumar et al., 2021; Pei et al., 2020). Implementing the error correction method of the proposed (4,2) compressor is straightforward, as the error distances of the proposed designs are ‘−1’ except for two input rows, as indicated in Table 2. Therefore, an Error Correction Module (ECM) is proposed, which produces ‘1’ and adds it to the next (4,2) compressor and Full Adder as a Cin at the same stage to rectify the proposed (4,2) compressor’s error distance shown in Figure 17. The proposed ECM is operated based on (7); the formula is obtained from the canonical form of a Karnaugh map consisting of rows with ‘−1’ error distance in the truth table of the proposed (4,2) compressors (Table 2). The compression process of an unsigned 8 × 8 multiplier with Dadda tree structure using (4,2) compressor, Full Adder, and Half Adder blocks is illustrated in Figure 17.
Design and Evaluation of Multipliers Using Simulated Annealing and Partitioning Approach
Published in IETE Journal of Education, 2023
Pavitra Y.J., Jamuna S., Manikandan J.
Traditional designs need design expertise and optimization of circuits using Boolean algebra, Karnaugh map and Shannon’s decomposition is limited to small circuits. Metaheuristic algorithms are used to find design alternatives and simplify through association rules that are not commonly used by human designers [11]. This approach faces the problem of scalability as the circuit realization time is strongly affected by the increase in a number of primary inputs. But they produce competitive results when compared to those created by traditional methods. Simulated annealing (SA) is a metaheuristic which is used to deal with highly nonlinear problems and find a global minimum [12]. It is more suitable to hard discrete problems [13, 14] and the multiplier is considered a discrete, nonlinear problem.
New modified-majority voter-based efficient QCA digital logic design
Published in International Journal of Electronics, 2019
Ali Newaz Bahar, Firdous Ahmad, Shahjahan Wani, Safina Al-Nisa, Ghulam Mohiuddin Bhat
A new multifunctional gate called the MMV has been proposed using QCA. The schematic symbol representation of the proposed MMV is shown in Figure 5(a). The MMV gate is a powerful technique in terms of implementing efficient QCA logic circuits. Using the Karnaugh map, we can find the logic function of the MMV gate and is worked out as: